莱迪思解决方案

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  • Lattice mVision MIPI Video Sensor to PCIe Bridge Demonstration

    演示

    Lattice mVision MIPI Video Sensor to PCIe Bridge Demonstration

    This design demonstrates the functionality of transferring MIPI CSI-2 sensor video data to a computer through PCIe with a Direct Memory Access (DMA) engine.
    Lattice mVision MIPI Video Sensor to PCIe Bridge Demonstration
  • SLVS-EC传感器到PCIe桥接参考设计

    Reference Design

    SLVS-EC传感器到PCIe桥接参考设计

    该参考设计通过高速接口从CMOS图像传感器接收串行数据,并将其转换为DMA/PCIe子系统数据格式。
    SLVS-EC传感器到PCIe桥接参考设计
  • SLVS-EC传感器到PCIe桥接演示

    演示

    SLVS-EC传感器到PCIe桥接演示

    SLVS-EC RX IP为FPGA提供了一个接收CMOS图像传感器串行数据的接口,并将传入的串行数据转换为并行像素数据格式。
    SLVS-EC传感器到PCIe桥接演示
  • 莱迪思mVision MIPI视频传感器到PCIe桥接参考设计

    Reference Design

    莱迪思mVision MIPI视频传感器到PCIe桥接参考设计

    该演示将传感器数据传输到计算机存储器,并使用软件驱动将数据渲染为视频,在计算机屏幕上显示。
    莱迪思mVision MIPI视频传感器到PCIe桥接参考设计
  • Scatter-Gather 直接存储器访问(DMA)控制器

    IP Core

    Scatter-Gather 直接存储器访问(DMA)控制器

    通过scatter-gather功能实现可配置、多通道、符合WISHBONE规范的DMA控制器
    Scatter-Gather 直接存储器访问(DMA)控制器
  • IDE/ATA接口控制器

    Reference Design

    IDE/ATA接口控制器

    Implements a generic IDE interface controllercompliant with the ATA/ATAPI-5 Standard
    IDE/ATA接口控制器
  • GRCAN - CAN 2.0B Controller IP Core

    IP Core

    GRCAN - CAN 2.0B Controller IP Core

    The GRCAN core is a CAN controller with an AHB DMA backend. The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages in memory external to the CAN controller.
    CAN, AHB, DMA 
    GRCAN - CAN 2.0B Controller IP Core
  • GRHSSL - High Speed Serial Link Controller IP Core

    IP Core

    GRHSSL - High Speed Serial Link Controller IP Core

    The GRHSSL IP is a highly configurable high-speed serial link controller, described in VHDL. It can implement a SpaceFibre controller, a WizardLink controller or both.
    GRHSSL - High Speed Serial Link Controller IP Core
  • GRPCI IP Core

    IP Core

    GRPCI IP Core

    The GRPCI IP core provides a 32-bit master/target interface for AMBA AHB 2.0 systems. It includes parameterizable FIFOs for both master and target operation and can optionally be provided with an independent DMA engine.
    GRPCI IP Core
  • GRUSBDC - USB 2.0 Device Controller IP Core

    IP Core

    GRUSBDC - USB 2.0 Device Controller IP Core

    GRUSBDC provides an interface between an USB 2.0 bus and an AMBA-AHB 2.0 bus. The core is used for implementing USB 2.0 functions providing access to the USB through either an AHB slave or an AHB master interface.
    GRUSBDC - USB 2.0 Device Controller IP Core
  • AXI to PCIe Bridge IP Core

    IP Core

    AXI to PCIe Bridge IP Core

    The AXI to PCIe Bridge IP core translates AXI4 into PCIe transactions for shared memory or peer-to peer-applications. It is based on the Lattice PCIe Hard IP.
    AXI to PCIe Bridge IP Core
  • WinDriver – a driver development toolkit

    Reference Design

    WinDriver – a driver development toolkit

    WinDriver accelerates development and removes complexity, enabling fast, reliable PCI/PCIe/USB driver creation without kernel coding across Windows & Linux.
    WinDriver – a driver development toolkit
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