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  • Lattice mVision MIPI Video Sensor to PCIe Bridge Demonstration

    Demo

    Lattice mVision MIPI Video Sensor to PCIe Bridge Demonstration

    This design demonstrates the functionality of transferring MIPI CSI-2 sensor video data to a computer through PCIe with a Direct Memory Access (DMA) engine.
    Lattice mVision MIPI Video Sensor to PCIe Bridge Demonstration
  • Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design

    Reference Design

    Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design

    Reference Design that shows transfer of sensor data to the computer memory and rendering of the data as video on the computer screen using the software driver.
    Lattice mVision MIPI Video Sensor to PCIe Bridge Reference Design
  • SLVS-EC Sensor to PCIe Bridge Demonstration

    Demo

    SLVS-EC Sensor to PCIe Bridge Demonstration

    The SLVS-EC RX IP provides the FPGA an interface to receive serial data from CMOS Image Sensors and offers a solution to convert the incoming serial data to a parallel pixel data format.
    SLVS-EC Sensor to PCIe Bridge Demonstration
  • SLVS-EC Sensor to PCIe Bridge Reference Design

    Reference Design

    SLVS-EC Sensor to PCIe Bridge Reference Design

    SLVS-EC to PCIe reference design allows the quick interface to receive serial data from CMOS Image Sensors & convert to DMA/PCIe Subsystem data format.
    SLVS-EC Sensor to PCIe Bridge Reference Design
  • Scatter-Gather DMA Controller

    IP Core

    Scatter-Gather DMA Controller

    Implements a configurable, multi-channel, WISHBONE-compliant DMA controller with scatter-gather capability
    Scatter-Gather DMA Controller
  • IDE/ATA Interface Controller

    Reference Design

    IDE/ATA Interface Controller

    Implements a generic IDE interface controllercompliant with the ATA/ATAPI-5 Standard
    IDE/ATA Interface Controller
  • GRCAN - CAN 2.0B Controller IP Core

    IP Core

    GRCAN - CAN 2.0B Controller IP Core

    The GRCAN core is a CAN controller with an AHB DMA backend. The APB bus is used for configuration, control and status handling and the AHB bus is used for retrieving and storing CAN messages in memory external to the CAN controller.
    CAN, AHB, DMA 
    GRCAN - CAN 2.0B Controller IP Core
  • GRHSSL - High Speed Serial Link Controller IP Core

    IP Core

    GRHSSL - High Speed Serial Link Controller IP Core

    The GRHSSL IP is a highly configurable high-speed serial link controller, described in VHDL. It can implement a SpaceFibre controller, a WizardLink controller or both.
    GRHSSL - High Speed Serial Link Controller IP Core
  • GRPCI IP Core

    IP Core

    GRPCI IP Core

    The GRPCI IP core provides a 32-bit master/target interface for AMBA AHB 2.0 systems. It includes parameterizable FIFOs for both master and target operation and can optionally be provided with an independent DMA engine.
    GRPCI IP Core
  • GRUSBDC - USB 2.0 Device Controller IP Core

    IP Core

    GRUSBDC - USB 2.0 Device Controller IP Core

    GRUSBDC provides an interface between an USB 2.0 bus and an AMBA-AHB 2.0 bus. The core is used for implementing USB 2.0 functions providing access to the USB through either an AHB slave or an AHB master interface.
    GRUSBDC - USB 2.0 Device Controller IP Core
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