SLVS-EC Sensor to PCIe Bridge Demonstration

Supported by Multi-Protocol PCS Soft IP

The SLVS-EC RX IP provides the FPGA an interface to receive serial data from CMOS Image Sensors and offers a solution to convert the incoming serial data to a parallel pixel data format. This can receive up to eight lanes of differential serial data running at a maximum of 5 Gbps per lane. The SLVS-EC functions defined by the PHY Layer are supported by the Multi-Protocol PCS (MPCS) soft IP which instantiates the PMA/PCS IPs, and the Link Layer functions defined by the PHY Layer are supported.

Features

  • Compliant with SLVS-EC Protocol specification v2.0
  • Back compatibility with SLVS-EC Protocol specification v1.2
  • Supports PCIe Gen1, Gen2
  • Supports SLVS-EC RAW8 video format
Lattice mVision Solutions Stack

Block Diagram

Documentation

Quick Reference
Technical Resources
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
SLVS-EC Sensor to PCIe Bridge with CertusPro-NX Reference Design and Demonstration - User Guide
FPGA-RD-02261 1.0 9/27/2022 PDF 1.3 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
SLVS-EC Sensor to PCIe Bridge with CertusPro-NX Reference Design and Demonstration - Source Code
FPGA-RD-02261 1.0 9/27/2022 ZIP 10.8 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
SLVS-EC Sensor to PCIe Bridge with CertusPro-NX Demonstration - Bitstream
1.0 9/27/2022 BIT 1.9 MB
*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.