AXI to PCIe Bridge IP Core

Powerful PCIe communication with host main memory or other PCIe endpoints

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The AXI to PCIe Bridge IP core is Smartlogic’s IP solution with industry standard memory mapped AXI Interfaces. The IP core translates AXI4 memory read or writes to PCI-Express Transaction Layer Packets (TLPs) and translates PCIe memory read and write requests to AXI4 transactions

Features

  • No PCI Express protocol know-how required : The user only transmits valid AXI4 packets with payload
  • Fast and easy integration into user software : The supplied Linux or Windows Kernel Mode device drivers with comprehensive user manuals are designed for fast and easy integration into the user software.
  • Reference designs included : A Radiant demo design and C application are included and can be used as starting point for new designs
  • Support included for 6 months : The included support allows users to get help from our technical support
  • AXI4 Slave interface to initiate data transfers AXI to PCIe
  • Up to 8 AXI 4 Masters interfaces to receive transfers from PCIe
  • Low logic footprint, fits into small devices
  • Based on Lattice PCIe Hard IP

Block Diagram

AXI-Bridge Block Diagram放大图片

Diagram

  • 1 S-AXI and up to 8 M-AXI interfaces
  • Asynchronous clock input for each interface

Ordering Information

This IP core can be shipped as source code or encrypted source code.You can download the product brief from https://www.smartlogic.de/en/produkt/axi-bridge-for-pcie-ip-core/

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