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  • ​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​

    Reference Design

    ​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​

    USB to IO Bridging Reference Design Create plug-and-play peripheral expansion on USB-enabled FPGA & signal protocol conversion from USB to I2C, SPI, & GPIO.
    CrossLink-NX 
    USB, USB2, USB3, I2C, SPI, JTAG, LVDS, SLVS, FTDI 
    ​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​
  • CrossLinkU-NX Evaluation Board

    Board

    CrossLinkU-NX Evaluation Board

    CrossLinkU-NX Evaluation Board is a platform for general purpose application development using CrossLinkU-NX device, the first FPGA with hard USB2/3 (5Gbps) interface.
    CrossLink-NX 
    USB, USB2, USB3, I2C, SPI, JTAG, LVDS, SLVS, FTDI 
    CrossLinkU-NX Evaluation Board
  • USB 2.0/3.2 IP Core

    IP Core

    USB 2.0/3.2 IP Core

    Lattice USB 2.0/3.2 IP Core provides a solution to interface with a USB host and can be targeted to the Lattice CrossLink-NX FPGA Devices.
    CrossLink-NX 
    USB, USB2, USB3, AHB, AHB-L, AHB-Lite, AXI, I2C, SPI, JTAG, LVDS, SLVS, FTDI 
    USB 2.0/3.2 IP Core
  • USB 2.0 Device Controller IP Core (USB20SF)

    IP Core

    USB 2.0 Device Controller IP Core (USB20SF)

    USB20SF IP core provides FIFO interface for Data Endpoints while AHB Lite interface for Control Endpoint. This IP core supports High Speed and Full Speed modes
    CrossLink-NX 
    ARM, RISC-V, Soft Processor, FMC, AHB, AHB-Lite, AXI, Camera, ULPI, USB2 
    USB 2.0 Device Controller IP Core (USB20SF)
  • USB 2.0 Device with FIFO Interface (USB20HF)

    IP Core

    USB 2.0 Device with FIFO Interface (USB20HF)

    USB20HF IP Core provides FIFO & ULPI interface. It supports High Speed and Full Speed functionality for 15 IN/OUT endpoints.
    CrossLink-NX, iCE40 UltraPlus, MachXO2 
    FMC, Data Communication, Camera, ULPI, USB2, FIFO 
    USB 2.0 Device with FIFO Interface (USB20HF)
  • GRUSBDC - USB 2.0 Device Controller IP Core

    IP Core

    GRUSBDC - USB 2.0 Device Controller IP Core

    GRUSBDC provides an interface between an USB 2.0 bus and an AMBA-AHB 2.0 bus. The core is used for implementing USB 2.0 functions providing access to the USB through either an AHB slave or an AHB master interface.
    CertusPro-NX, Certus-NX 
    AHB, AMBA, DMA, USB2 
    GRUSBDC - USB 2.0 Device Controller IP Core
  • GRUSBHC - USB 2.0 Host Controller IP Core

    IP Core

    GRUSBHC - USB 2.0 Host Controller IP Core

    The USB 2.0 Host Controller provides a link between the AMBA on-chip bus and the Universal Serial Bus (USB). The host controller supports High-, Full- and Low-Speed USB traffic. The core can handle up to 15 downstream ports, where each port can handle all three USB speeds.
    CertusPro-NX, Certus-NX 
    AHB, AMBA, USB2 
    GRUSBHC - USB 2.0 Host Controller IP Core
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