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  • ​​I/O Aggregation Over USB with CrossLinkU-NX Reference Design​

    Reference Design

  • USB 2.0/3.2 IP Core

    IP Core

    USB 2.0/3.2 IP Core

    Lattice USB 2.0/3.2 IP Core provides a solution to interface with a USB host and can be targeted to the Lattice CrossLink-NX FPGA Devices.
    USB 2.0/3.2 IP Core
  • CrossLinkU-NX USB3 Vision Reference Design

    Reference Design

    CrossLinkU-NX USB3 Vision Reference Design

    A design provides a template for video streaming from camera sensor over USB using the USB hard IP in a CrossLinkU-NX device.
  • ​​USB 3.2 Gen 1 Device Controller IP Core (USB32SF)​

    IP Core

    ​​USB 3.2 Gen 1 Device Controller IP Core (USB32SF)​

    This IP core solution uses the FPGA’s built-in transceiver for USB 3.2 and ULPI PHY for USB 2.0. It supports SuperSpeed, High Speed and Full Speed modes.
    ​​USB 3.2 Gen 1 Device Controller IP Core (USB32SF)​
  • ​​tinyCLUNX33 System on Module​

    Board

    ​​tinyCLUNX33 System on Module​

    ​​1x1" production ready, tightly integrated System on Module using Lattice CrossLinkU-NX (LIFCL-33U) to significantly reduce customers Time to Market.​
    ​​tinyCLUNX33 System on Module​
  • ​​USB 3.2 FMC Board​

    Board

    ​​USB 3.2 FMC Board​

    ​​USB 3.2 FMC Board is to validate USB 3.2 functionality with FPGA’s inbuilt serial transceivers. It has ULPI PHY chip to validate USB 2.0 functionality.​
    ​​USB 3.2 FMC Board​
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