USB 2.0/3.2 IP Core

USB 2.0/3.2 (5Gbps) Interface Innovation

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The Lattice Semiconductor USB 2.0/3.2 IP Core provides a solution to interface with the USB Host. The design is implemented using Verilog HDL. The IP Core can be targeted to the Lattice CrossLink-NX FPGA Devices. The IP Core is implemented using the Lattice Radiant Software integrated with the Synplify Pro synthesis tool.

Resource Utilization details are available in the Reference Design User Guide.

Features

  • Supports High Speed and Full Speed USB 2.0 specification and Super Speed USB 3.2 specification
  • Supports high-speed, high-bandwidth isochronous transactions
  • Supports two control endpoints at EP0/1 (1 IN 1 OUT) and eight individually reconfigurable logical endpoints. Each logical endpoint reflect two physical endpoints, one IN and one OUT endpoint.
  • Includes an example design as a reference usage model

Block Diagram

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
CrossLink-NX USB-CNX-UT USB-CNX-US

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
USB 2.0/3.2 IP User Guide
FPGA-IPUG-02237 1.2 12/20/2024 PDF 4.8 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
USB 2.0/3.2 IP Release Notes
FPGA-RN-02037 1.0 12/20/2024 PDF 210.5 KB

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