The Lattice Semiconductor USB 2.0/3.2 IP Core provides a solution to interface with the USB Host. The design is implemented using Verilog HDL. The IP Core can be targeted to the Lattice CrossLink-NX FPGA Devices. The IP Core is implemented using the Lattice Radiant Software integrated with the Synplify Pro synthesis tool.
Resource Utilization details are available in the Reference Design User Guide.