USB 2.0/3.2 IP Core

USB 2.0/3.2 (5Gbps) Interface Innovation

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The Lattice Semiconductor USB 2.0/3.2 intellectual property (IP) core provides a solution to interface with the USB host. The design is implemented using Verilog HDL. The IP core is targeted for Lattice CrossLinkU™-NX FPGAs. The IP core is implemented using the Lattice Radiant™ software integrated with the Synopsys® Synplify Pro® synthesis tool.

The Lattice USB 2.0/3.2 IP core supports the USB-IF compliant USB standard.

Resource Utilization details are available in the Reference Design User Guide.

Features

  • Supports High Speed and Full Speed USB 2.0 specification and Super Speed USB 3.2 specification
  • Supports high-speed, high-bandwidth isochronous transactions
  • Supports two control endpoints at EP0/1 (1 IN 1 OUT) and eight individually reconfigurable logical endpoints. Each logical endpoint reflect two physical endpoints, one IN and one OUT endpoint.
  • Includes an example design as a reference usage model

Block Diagram

USB 2.0/3.2 IP Core Block DiagramExpand Image

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
CrossLinkU-NX USB-CNX-UT USB-CNX-US

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
USB 2.0/3.2 IP Core - User Guide
FPGA-IPUG-02237 1.3 4/7/2025 PDF 5.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
USB 2.0/3.2 IP Core - Release Notes
FPGA-RN-02037 1.1 4/7/2025 PDF 186.5 KB

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