USB 2.0/3.2 IP Core

USB 2.0/3.2 (5Gbps) Interface Innovation

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The Lattice Semiconductor USB 2.0/3.2 IP Core provides a solution to interface with the USB Host. The design is implemented using Verilog HDL. The IP Core can be targeted to the Lattice CrossLink-NX FPGA Devices. The IP Core is implemented using the Lattice Radiant Software integrated with the Synplify Pro synthesis tool.

Compliant with USB-IF USB Standards – USB 2.0/3.2 supports USB Interface, compliant with USB-IF USB standards.

Reduced Effort to Integrate the USB 2.0/3.2 – The USB 2.0/3.2 IP Core reduces the effort required to integrate the USB 2.0/3.2.

Simplified User Application Design – Primitive with the user application design and minimizes the need to directly deal with the USB 2.0/3.2 by providing AHB Data Interface.

Features

  • Supports High Speed and Full Speed USB 2.0 specification and Super Speed USB3.2 specification
  • Supports high speed, high bandwidth isochronous transactions
  • Supports up to 16 endpoints, including one control endpoint 0. Endpoints 1 to 15 can be bulk, interrupt, or isochronous and are individually configurable
  • Example Design included as a reference usage model

Resource Utilization details are available in the IP User Guide.

Block Diagram

USB 2.0/3.2 IP Core Block DiagramExpand Image

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
CrossLink-NX USB-CNX-UT USB-CNX-US

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
USB 2.0/3.2 IP Core – User Guide
FPGA-IPUG-02237 1.1 3/29/2024 PDF 4.4 MB

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