USB 2.0/3.2 IP Core

USB 2.0/3.2 (5Gbps) Interface Innovation

The Lattice Semiconductor first release of USB 2.0 Soft IP Core provides a solution to interface with a USB Host. The design is implemented using Verilog HDL. The IP Core can be targeted to the Lattice CrossLinkU-NX FPGA Devices. The IP Core is implemented using the Lattice Radiant Software integrated with the SynplifyPro synthesis tool.

The USB 2.0 Soft IP Core reduces the effort required to integrate the USB 2.0 Primitive with the user application design and minimizes the need to directly deal with the USB 2.0 by providing AHB Data Interface.

High Speed and Full Speed – Supports USB 2.0 HS (480 Mbps) and FS (12 Mbps).

Compliant to USB Standards – Supports up to eight endpoints, including one control endpoint 0. Endpoints 1 to 7 can be bulk, interrupt, or isochronous and are individually configurable.

Features

  • Supports High Speed and Full Speed USB 2.0 specification
  • Supports high speed, high bandwidth isochronous transactions
  • Supports up to 16 endpoints, including one control endpoint 0. Endpoints 1 to 15 can be bulk, interrupt, or isochronous and are individually configurable
  • Example Design included as a reference usage model

Block Diagram

Resource Utilization

CrossLink-NX (LIFCL-33U-8CTG104C)
Configuration LUTs Registers EBRs USB Hard Block
For all address configurations 1167 796 8 1

Ordering Information

Device Family Multi-Site Perpetual Single Machine Annual License
CrossLink-NX USB-CNX-UT USB-CNX-US

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
USB 2.0/3.2 IP Core - User Guide
FPGA-IPUG-02237 1.0 10/11/2023 PDF 2.2 MB

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