​​USB 3.2 Gen 1 Device Controller IP Core (USB32SF)​

​​FPGA-Based SLS IP Core Supporting USB 3.2 SuperSpeed and USB 2.0 ULPI PHY​

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USB32SF IP core is designed to use the Lattice® Semiconductor FPGA built-in transceiver ensuring highest throughput i.e. >3.4Gbps.

Features

  • It supports SuperSpeed (SS), High Speed (HS) and Full Speed (FS) communication modes.
  • Uses Lattice FPGA Transceiver as a PHY layer and thus eliminates need for external PHY for USB 3.2.
  • Provides ULPI interface to interact with external USB 2.0 PHY.
  • Capable to support up to 31 endpoints (1 default control endpoint, 15 IN endpoints and 15 OUT endpoints).
  • Allows to select number of buffers per endpoint based on the requirement.

Block Diagram

​​USB 3.2 Gen 1 Device Controller IP Core Block DiagramExpand Image

Ordering Information

Get one-month free evaluation license from IP Evaluation Request - System Level Solutions (slscorp.com). Write us at info@slscorp.com.

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