1 Performance and utilization characteristics are generated using an OR4E042BA352 in ispLEVERTM software v.3.0. Synthesized using Synplicity Synplify, v.7.0.3. When using this IP core in different density, package, speed, or grade within the ORCA 4 family, performance may vary slightly.
2 LUT is a standard logic block of some Lattice devices. For more information, check the data sheet of the device.
1 Performance and Utilization characteristics are generated using LFX500B-04F516C. When using this IP core in different density, package, speed, or grade within the ispXPGA family, performance may vary slightly.
2 PFU is a standard logic block of some Lattice devices. For more information, refer to the data sheet of the device.
1 Performance and utilization characteristics are generated using LFEC20E-5F672C in Lattice’s ispLEVER v.4.1 software. When using this IP core in a different device, density, package, or speed grade, performance may vary.
2 The I/Os for these configurations include the optional signals d_del and err_cnt. The width of the err_cnt signal bus is 5 for the CCSDS configuration, and 4 for the other evaluation configurations.