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  • TICO-RAW Encoder/Decoder IP-cores

    IP Core

    TICO-RAW Encoder/Decoder IP-cores

    TICO-RAW is a revolutionary RAW compression, extremely tiny & low power, with low latency and lossless quality to handle camera and sensor data (Bayer).
    TICO-RAW Encoder/Decoder IP-cores
  • TICO-XS (JPEG XS) Encoder / Decoder IP-cores

    IP Core

    TICO-XS (JPEG XS) Encoder / Decoder IP-cores

    JPEG XS is the new revolutionary codec, extremely tiny in Lattice FPGA, robust for real-time operation with zero latency and lossless quality
    TICO-XS (JPEG XS) Encoder / Decoder IP-cores
  • Tri-Rate Serial Digital Interface Physical Layer

    IP Core

    Tri-Rate Serial Digital Interface Physical Layer

    A complete SDI PHY SERDES-based interface bridging high-speed SDI serial data to formatted parallel video data. Compliant to numerous SMPTE standards.
    Tri-Rate Serial Digital Interface Physical Layer
  • Digital Video Broadcasting - (DVB-ASI) IP Core

    IP Core

    Digital Video Broadcasting - (DVB-ASI) IP Core

    Implements Layer 1 of the DVB-ASI interface (using LatticeECP3 SERDES/PCS) plus a part of Layer 2 functionality.
    Digital Video Broadcasting - (DVB-ASI) IP Core
  • H.264-ENC1: Enciris Technologies H264-HD encoder

    IP Core

    H.264-ENC1: Enciris Technologies H264-HD encoder

    A high performance HD compression core IP that implements the H.264 (MPEG-4/AVC) video coding standard
    H.264-ENC1: Enciris Technologies H264-HD encoder
  • Dynamic Block Reed-Solomon Decoder

    IP Core

    Dynamic Block Reed-Solomon Decoder

    Highly configurable, and compliant with several industry standards including IEEE 802.16-2004
    Dynamic Block Reed-Solomon Decoder
  • Dynamic Block Reed-Solomon Encoder

    IP Core

    Dynamic Block Reed-Solomon Encoder

    Used to perform Forward Error Correction (FEC) in data communications and digital video broadcasting. Highly configurable.
    Dynamic Block Reed-Solomon Encoder
  • Common Scrambling Algorithm Cores

    IP Core

    Common Scrambling Algorithm Cores

    Implement the ETSI specified Common Scrambling Algorithm (CSA) which is used to provide the conditional access mechanism for MPEG-2 video streams
    Common Scrambling Algorithm Cores
  • Multi-Rate Serial Digital Interface PHY Layer

    IP Core

    Multi-Rate Serial Digital Interface PHY Layer

    A complete SDI PHY interface that connects high-speed SDI serial data to formatted parallel data. It supports SMPTE standards
    Multi-Rate Serial Digital Interface PHY Layer
  • LatticeECP2M SMPTE SDI Evaluation Board

    Board

    LatticeECP2M SMPTE SDI Evaluation Board

    No longer available - for reference only. For development and evaluation of the LatticeECP2M in video applications. + SERDES interfaces for SMPTE 259 and 292.
    LatticeECP2M SMPTE SDI Evaluation Board
  • LT-125 Video Codec Evaluation Platform

    Board

    LT-125 Video Codec Evaluation Platform

    A LatticeECP3 based HD video compression and decompression evaluation platform
    LT-125 Video Codec Evaluation Platform
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