ECC Module Reference Design

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Reference Design LogoThis reference design implements an Error Correction Code (ECC) module for the LatticeEC™ and LatticeSC™ FPGA families that can be applied to increase memory reliability in critical applications. The ECC module provides Single Error Correction - Double Error Detection (SECDED) capability based on a class of optimal minimum oddweight error parity codes that provides better performance than typical Hamming-based SECDED codes. Several architecture options are identified that allow the user to optimally tailor the speed, resource utilization, and latency of the module implementation to their specific application requirements.

Features

  • SECDED capability implemented using an optimal odd-weight parity matrix that provides better performance than typical Hamming-based codes
  • Directly usable code for a (72,64) SECDED module provided. Specifications provided for similar (22,16) and (39,32) modules
  • Separate registered encoder and decoder modules to support optimized integration with user logic
  • Optional pipelining implementation to provide increased maximum speed of operation
  • Error insertion/error indication diagnostic capabilities

Jump to

Block Diagram

Performance and Size

Device Configuration Resource Utilization (Slices/LUTs/ Regs) fMAX
LFEC20, -5 Non-pipelined 267/388/350 130MHz
LFEC20, -5 Pipelined 329/378/496 215MHz
LFEC20, -5 Non-registered, logic only 120/237/0 -

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
ECC Module
RD1025 01.1 10/16/2012 PDF 918.1 KB
ECC Module - Source Code
RD1025 1.1 10/16/2012 ZIP 386 KB

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