XAUI 10Gb Ethernet Attachment Unit Interface


Newsletter Subscription

IP Express10Gb Ethernet Attachment Unit Interface or XAUI is a high-speed interconnect that offers reduced pin count and has the ability to drive up to 20 inches of PCB trace on standard FR-4 material. Each XAUI interface comprises four self-timed 8b10b encoded serial lanes each operating at 3.125 Gbps and thus is capable of transferring data at an aggregate rate of 10 Gbps.

XAUI IP Core provides a solution for bridging between XAUI and 10 Gigabit Media Independent Interface (XGMII) devices. This IP core implements 10Gb Ethernet Extended Sublayer (XGXS) capabilities in soft logic that together with PCS and SERDES functions implemented in the FPGA provides a complete XAUI-to-XGMII solution.

Features

  • XAUI compliant functionality supported by embedded SERDES PCS functionality implemented in the LatticeECP2M and LatticeECP3, including four channels of 3.125 Gbps serializer/deserializer with 8b10b encoding/decoding.
  • Complete 10Gb Ethernet Extended Sublayer (XGXS) solution based on LatticeECP2M and LatticeECP3 FPGA.
  • Soft IP targeted to the FPGA implements XGXS functionality conforming to IEEE 802.3ae-2002, including:
    • 10 GbE Media Independent Interface (XGMII).
    • Optional Slip buffers for clock domain transfer to/from the XGMII interface.
    • Complete translation between XGMII and XAUI PCS layers, including 8b10b encoding and decoding of Idle, Start, Terminate, Error and Sequence code groups and sequences, and randomized Idle generation in the XAUI transmit direction.
    • XAUI compliant lane-by-lane synchronization.
    • Lane deskew functionality.
    • Interface with the high-speed SERDES block embedded in the LatticeECP2M and LatticeECP3 that implements a standard XAUI.
    • Optional standard compliant MDIO/MDC interface.
  • Aldec and ModelSim simulation models and test benches provided for free evaluation.

Lattice's IP hardware evaluation capability makes it possible to create versions of IP cores that operate in hardware for a limited time of four hours without requiring the purchase on an IP license. The hardware evaluation capability is turned on by enabling the Hardware Evaluation option in the properties of the Build Database process in ispLEVER. If a license is detected, core generation is completed with no restrictions.

Jump to

Block Diagram

XAUI Protocol Stack XAUI Block Diagram

Performance and Size

ECP51
Configuration Utilization
Device TX Slip
Buffer		 RX Slip
Buffer		 MDIO SLICEs LUTs Registers EBRs
LFE5UM-45F-7BG554C No No No 1472 2263 1624 0
LFE5UM-85F-7BG756C Yes Yes Yes 2511 3080 3225 4

1. Performance and utilization data are generated using Lattice Diamond 3.3 and Synplify Pro for Lattice F-2014.03L-SP1 beta software. Performance may vary when using a different software version or targeting a different device density or speed grade within the ECP5 family.

LatticeECP31
Configuration Utilization
Device TX Slip
Buffer		 RX Slip
Buffer		 MDIO SLICEs LUTs Registers EBRs
LFE3-35E-7FN484CES No No No 1194 1674 1498 0
LFE3-70E-7FN672CES No Yes No 1529 2077 1980 2
LFE3-150E-7FN1156CES Yes Yes No 1880 2510 2467 4

1. Performance and utilization data are generated using Lattice Diamond 1.0 and Synplify Pro for Lattice D-2009.12L software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP3 family.

LatticeECP2M/S1
Configuration Utilization
Device TX Slip
Buffer		 RX Slip
Buffer		 MDIO SLICEs LUTs Registers EBRs
LFE2M20E-6F256CES No No No 1351 1813 1545 0
LFE2M20E-6F256CES No No Yes 1447 1951 1685 0
LFE2M35E-6F484CES No Yes No 1632 2137 1989 2
LFE2M50E-6F672CES Yes No No 1727 2264 2033 2
LFE2M70E-6F900CES Yes Yes Yes 2160 2801 2641 4

1. Performance and utilization data are generated using Lattice Diamond 1.0 and Synplify Pro for Lattice D-2009.12L software. Performance may vary when using a different software version or targeting a different device density or speed grade within the LatticeECP2M family.

Ordering Information

Family Part Number
ECP5 XAUI-E5-U
LatticeECP3 XAUI-E3-U1
LatticeECP2M XAUI-PM-U1

IP Version: 1.6.

Evaluate: To download a full evaluation version of this IP, go to the IPexpress tool and click the IP Server button in the toolbar. All LatticeCORE IP cores and modules available for download will be visible. For more information on viewing/downloading IP please read the IP Express Quick Start Guide.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LatticeECP3 and Marvell 10 Gbps Physical/MAC Layer Interoperability
TN1219 1.0 7/26/2010 PDF 1.4 MB
LatticeECP3 and Broadcom 10 Gbps Physical/MAC Layer Interoperability
TN1218 1.1 2/13/2012 PDF 3.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LatticeECP3 and Marvell 10 Gbps Physical/MAC Layer Interoperability
TN1219 1.0 7/26/2010 PDF 1.4 MB
LatticeECP3 and Broadcom 10 Gbps Physical/MAC Layer Interoperability
TN1218 1.1 2/13/2012 PDF 3.5 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
FPGA-IPUG-02160-XAUI-Ethernet-IP-Core-Radiant-SW
FPGA-IPUG-02160 1.0 10/25/2021 PDF 1.2 MB
LatticeECP3 and ECP5 XAUI IP Core User Guide
IPUG115 1.0 10/15/2014 PDF 3.8 MB
XAUI IP Core User's Guide
IPUG68 01.6 2/3/2012 PDF 885.2 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
IPexpress Quick Start Guide
8/5/2010 PDF 304.8 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

About Us

Sales

Support

 
 
 
 
 
 
Lattice QR code