The Lattice Semiconductor 10Gb Ethernet Attachment Unit Interface (XAUI) provides a solution for bridging between XAUI and 10-Gigabit Media Independent Interface (XGMII) devices. The IP core implements the 10Gb Ethernet Extended Sublayer (XGXS) capabilities in soft logic that together with PCS and SerDes functions implemented in the FGPA provides a complete XAUI-to-XGMII solution. XGMII is a 156.25 MHz Double Data Rate (DDR), parallel, short-reach interconnect interface. It supports interfacing to 10 Gbps Ethernet Media Access Control (MAC) and PHY devices.
High-speed Interconnect - XAUI is a high-speed interconnect that offers reduced pin count. Each XAUI comprises four self-timed 8b10b encoded serial lanes each operating at 3.125 Gbps and thus is capable of transferring data at an aggregate rate of 10 Gbps.
Supports Double Data Rate (DDR) Transmission - The XGMII supports Double Data Rate (DDR) transmission (that is the data and control input signals are sampled on both the rising and falling edge of the corresponding clock).