AHB-Lite Interconnect Module

AHB-Lite system interconnect

The Lattice Semiconductor AHB-Lite Interconnect Module is a fully parameterized soft IP for high performance, low latency interconnect fabric for AHB-Lite system. It can be used to connect one or more AHB-Lite bus master to one or more AHB-Lite bus slaves.

It allows multiple bus masters to access different slaves in parallel without the need for arbitration. Slave-side arbitration is implemented for each slave port of the module to maximize parallelism.

The AHB-Lite Interconnect module supports round-robin based and fixed priority based arbitration when multiple bus masters access the same slave port. The arbitration completes in one clock cycle, which mean the transaction will be delayed by one clock cycle when arbitration occurs.


  • Compliant with AMBA 3 AHB-Lite Protocol v1.0
  • Data bus width up to 1024 bits [8, 16, 32, 64, 128, 256, 512, 1024]
  • Address width up to 32-bits [11,12,...,32]
  • Supports up to 32 masters and 32 slaves
  • Supports fragmented address space up to eight fragments per Slave
Lattice Propel

Block Diagram

AHB-Lite Interconnect Module Block Diagram


Quick Reference
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AHBL Master BFM Lite VIP - Lattice Propel Builder
FPGA-IPUG-02148 1.0 12/8/2020 PDF 808.5 KB
AHB-Lite Interconnect Module - Lattice Propel Builder
FPGA-IPUG-02051 1.2 5/11/2021 PDF 958 KB

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