I3C Target IP Core

Monitors I3C Bus for Relevant I3C Commands Sent by the I3C Controller

The Lattice I3C IP Core is designed to comply with the MIPI I3C specification.

The I3C Controller accepts commands from a LMMI interface or APB/AHB-Lite if user selected the optional standard interface. These commands are translated into I3C signals and forwarded to I3C target Device. The I3C Controller can operate in interrupt or polling mode. This means that the user can choose to poll the I3C Controller for a change in status at periodic intervals or wait to be interrupted by the I3C Controller when data needs to be read or written.

Eases Sensor System Design Architectures - The MIPI I3C interface eases sensor system design architectures in mobile wireless products by providing a fast, low-cost, low-power, two-wire digital interface for sensors. I3C a single scalable, cost effective, power efficient protocol to solve issues with the high protocol overhead, power consumption, nonstandard protocol, separate lines for interrupt and the rest requirement.

Offers Greater Than 10x Speed Improvements - I3C offers greater than 10x speed improvements, more efficient bus power management, new communication Modes, and new Device roles, including an ability to change Device Roles over time

Supports Several Communication Formats - I3C Target IP supports several communication formats, all sharing a two-wire interface: SDA bidirectional data line and SCL input.

Features

  • Two-wire serial interface up to 12.5 MHz using Push-Pull
  • Legacy I2C Device co-existence on the same Bus (with some limitations)
  • Dynamic Addressing
  • I2C-like Single Data Rate messaging (SDR)
  • In-Band Interrupt and Hot-Join support

Block Diagram

Resource Utilization

LFCPNX-100-7ASG256C
Configuration clk Fmax (MHz) Registers LUTs EBRs DSPs
Default 104.26 725 1887 2 0
IBI Capable = False 95.22 660 1637 2 0
Hot-Join Capable = False 99.25 707 1842 2 0
IBI Capable = False,
Hot-Join Capable = False
100.17 627 1499 2 0

1. Fmax is generated when the FPGA design only contains the SDR module, and the target frequency is 200 MHz. These values may be reduced when user logic is added to the FPGA design.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

LIFCL-40-7BG256I
Configuration clk Fmax (MHz) Registers LUTs EBRs DSPs
Default 88.44 756 1832 2 0
IBI Capable = False 91.79 699 1555 2 0
Hot-Join Capable = False 98.16 707 1842 2 0
IBI Capable = False,
Hot-Join Capable = False
91.56 627 1499 2 0

1. Fmax is generated when the FPGA design only contains the SDR module, and the target frequency is 200 MHz. These values may be reduced when user logic is added to the FPGA design.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G I3C-S-AVG-UT I3C-S-AVG-US
Avant-X I3C-S-AVX-UT I3C-S-AVX-US
Avant-E I3C-S-AVE-UT I3C-S-AVE-US
CertusPro-NX I3C-S-CPNX-UT I3C-S-CPNX-US
CrossLink-NX I3C-S-CNX-UT I3C-S-CNX-US
MachXO5-NX I3C-S-XO5-UT I3C-S-XO5-US
Certus-NX I3C-S-CNX-UT I3C-S-CNX-US
iCE40 UltraPlus I3C-S-UP-UT I3C-S-UP-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice distributor or sales representative.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
I3C Target IP Core - User Guide
FPGA-IPUG-02227 1.2 12/5/2023 PDF 938.6 KB

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