I3C Target IP Core

Monitors I3C Bus for Relevant I3C Commands Sent by the I3C Controller

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The Lattice I3C Target IP core supports several communication formats, all sharing a two-wire interface: SDA bidirectional data line and SCL bidirectional clock. It monitors the I3C bus for relevant I3C commands sent by the I3C Controller and responds accordingly. Also, this IP accepts commands from LMMI or from the optional APB/AHB-Lite interface.

The Lattice I3C IP is designed to comply with the MIPI I3C specification. The MIPI I3C interface eases sensor system design architectures in mobile wireless products by providing a fast, low-cost, low-power, two-wire digital interface for sensors. I3C protocol is a single scalable, cost effective, and a power efficient protocol. Implementing the I3C specification greatly increases the implementation flexibility for an ever-expanding sensor subsystem as efficiently and at as low cost as possible.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Compatible with MIPI I3C Specification v1.1.1
  • Two-wire serial interface up to 12.5 MHz using Push-Pull
  • Legacy I2C device co-existence on the same bus (with some limitations)
  • Dynamic Addressing with optional Static Addressing for I3C Target acting as I2C Target
  • I2C -like SDR messaging

Block Diagram

I3C Target Block DiagramExpand Image

Resource Utilization

LFCPNX-100-7ASG256C
Configuration clk Fmax (MHz) Registers LUTs EBRs DSPs
Default 104.26 725 1887 2 0
IBI Capable = False 95.22 660 1637 2 0
Hot-Join Capable = False 99.25 707 1842 2 0
IBI Capable = False,
Hot-Join Capable = False 		100.17 627 1499 2 0

1. Fmax is generated when the FPGA design only contains the SDR module, and the target frequency is 200 MHz. These values may be reduced when user logic is added to the FPGA design.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

LIFCL-40-7BG256I
Configuration clk Fmax (MHz) Registers LUTs EBRs DSPs
Default 88.44 756 1832 2 0
IBI Capable = False 91.79 699 1555 2 0
Hot-Join Capable = False 98.16 707 1842 2 0
IBI Capable = False,
Hot-Join Capable = False 		91.56 627 1499 2 0

1. Fmax is generated when the FPGA design only contains the SDR module, and the target frequency is 200 MHz. These values may be reduced when user logic is added to the FPGA design.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

Ordering Information

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G I3C-S-AVG-UT I3C-S-AVG-US
Avant-X I3C-S-AVX-UT I3C-S-AVX-US
Avant-E I3C-S-AVE-UT I3C-S-AVE-US
CertusPro-NX I3C-S-CPNX-UT I3C-S-CPNX-US
CrossLink-NX I3C-S-CNX-UT I3C-S-CNX-US
MachXO5-NX I3C-S-XO5-UT I3C-S-XO5-US
Certus-NX I3C-S-CNX-UT I3C-S-CNX-US
iCE40 UltraPlus I3C-S-UP-UT I3C-S-UP-US
Bundled MIPI-BUNDL-UT MIPI-BUNDL-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

Purchase: To find out how to purchase the IP Core, please contact your local Lattice distributor or sales representative.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
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I3C Target Driver API Reference
FPGA-TN-02338 1.0 12/21/2023 PDF 769.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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I3C Target Driver API Reference
FPGA-TN-02338 1.0 12/21/2023 PDF 769.7 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
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I3C Target IP Core - User Guide
FPGA-IPUG-02227 1.3 6/28/2024 PDF 2 MB

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