MachXO5-NX LFMXO5-55TD Soft BSCAN Reference Design

Soft JTAG Boundary-Scan Setup for MachXO5-55TD with Manual VCCIO Configuration

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​​The Lattice Semiconductor MachXO5™-NX LFMXO5-55TD (also referred to as MachXO5-NX-55TD or MachXO5-55TD) soft boundary-scan (BSCAN) reference design enables boundary scan testing through a soft JTAG interface to enhance device security, external access to the hardware JTAG port is disabled. Therefore, board-level boundary scan testing must be performed using the soft JTAG boundary-scan IP core.

Features

  • The soft BSCAN reference design provides the test access port (TAP) and boundary-scan architecture based on IEEE 1149.1 (IEEE Standard for Test Access Port and Boundary-Scan Architecture).
  • The soft BSCAN reference design includes following blocks:
    • OSC IP
    • PLL IP
    • SFB Module
    • Soft BSCAN IP

Block Diagram

BD_MachXO5-NX LFMXO5-55TD Soft BSCAN Reference Design Block DiagramExpand Image

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
MachXO5-NX LFMXO5-55TD Soft BSCAN Reference Design – Source Code
1.0 6/18/2025 ZIP 106.4 MB
MachXO5-NX LFMXO5-55TD Soft BSCAN Reference Design – User Guide
FPGA-RD-02315 1.0 6/18/2025 PDF 1.2 MB

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