Lattice Sentry SMBus Mailbox IP Core

System Management Bus IP Core

The System Management Bus (SMBus) is a two-wire interface that provides a simple and efficient method of communication with the rest of the system. It is compatible with I2C bus protocol and is often found in monitoring power conditions, temperature, and other sensors on a board.

SMBus Mailbox is a SMBus slave, which is designed to communicate with SMBus host mailbox. It responds to the standard SMBus Write Byte and Read Byte format messages.

Master Controller supports multi-master on one bus simultaneously - All the masters obey fairness arbitration rules to avoid any bus conflicts.

SMBus bus protocols support many kinds of formats - such as SMBus write byte, SMBus write word, SMBus read byte, SMBus read word, SMBus write block, and SMBus read block.


  • Compatible with SMBus and AHB-Lite Specification
  • Supports 7-bit/10-bit addressing modes
  • Clock stretching and wait state generation
  • Interrupt flag generation
  • Arbitration lost interrupt, with automatic transfer cancellation

Block Diagram


Quick Reference
Select All
Lattice Sentry SMBus Mailbox IP Core – User’s Guide
FPGA-IPUG-02165 1.0 12/14/2021 PDF 1 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.