PIC IP Core

Programmable Interrupt Controller IP Core

The Lattice Semiconductor PIC soft IP is a programmable interrupt controller 1~8 interrupt inputs and all register can be accessed through 32-bit AHB-L interface. The number of interrupt inputs is configurable and interrupt status, masks, and polarities are programmable.

The design is implemented in Verilog HDL. It can be configured and generated using the Lattice Propel™ Builder software. It can be targeted to Mach-NX™ FPGA devices and implemented using the Lattice Diamond® software Place and Route tool integrated with the Synplify Pro® synthesis tool.

Aggregates up to eight external interrupt inputs - PIC aggregates up to eight external interrupt inputs (IRQs) into one interrupt output to processor core. The interrupt status register can be used to read the values of IRQs. Individual IRQs can be configured by programming the corresponding PIC_STATUS, PIC_ENABLE, PIC_SET, and PIC_POL registers.

Lattice Propel Builder Support – This IP Core is implemented in Verilog HDL targeted to Mach-NX FPGA Devices.

Features

  • 1~8 interrupt inputs
  • Programmable interrupt status, masks, and polarities
  • Attributes can be configured through the Propel Builder software
  • Support for the AHB-L bus standard for register read/write
  • Support for Mach-NX

Block Diagram

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Lattice Sentry Programmable Interrupt Controller IP Core - User's Guide
FPGA-IPUG-02141 1.0 12/16/2021 PDF 922 KB

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