Lattice Sentry QSPI Streamer IP Core for MachXO3D

Resilient SPI/QSPI Security IP for Platform Firmware Resiliency

Related Products

Configurable SPI master – Supports SPI and QSPI slaves.

Designed for Performance – Programmable length read and write transactions allow an entire SPI flash to be read in one SPI transaction.

Tested and Fully Validated – This resilient IP is a pre-built security component which is part of the Lattice Sentry Platform Root of Trust solution stack. No FPGA experience or RTL programming is necessary to implement this into your Platform Root of Trust design.


  • Provides fast SPI memory access for firmware authentication as part of Platform Root of Trust operation
  • Support for AMBA 3 APB Protocol v1.0 for RISC-V CPU access
  • Configurable using Lattice Propel: no FPGA design or modification necessary
  • Controllable by modifying included reference C source code, which runs on interal RISC-V CPU
  • Pin location and pin-out can be selected visually using Lattice Propel to optimize board design; no RTL programming necessary
Lattice Sentry

Block Diagram

QSPI Streamer IP Block Diagram


Quick Reference
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Lattice Sentry QSPI Streamer - User's Guide
FPGA-IPUG-02109 1.0 8/12/2020 PDF 971.5 KB

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