Configurable SPI master – Supports SPI and QSPI slaves.
Designed for Performance – Programmable length read and write transactions allow an entire SPI flash to be read in one SPI transaction.
Tested and Fully Validated – This resilient IP is a pre-built security component which is part of the Lattice Sentry Platform Root of Trust solution stack. No FPGA experience or RTL programming is necessary to implement this into your Platform Root of Trust design.