​​RISC-V MC and DDR3 Memory Controller Reference Design​

​​Enabling the RISC-V MC in Certus™-NX Device to Interface with DDR3 Memory Controller​

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​​The RISC-V MC and DDR3 Memory Controller Reference Design provides an example usage of the RISC-V MC soft IP and DDR3 memory controller in Certus™ NX FPGA devices.

The Lattice Semiconductor RISC-V MC CPU contains a 32-bit RISC-V processor core and several submodules – Timer and Programmable Interrupt Controller (PIC). The CPU core supports the RV32IMC instruction set and debug feature, which is JTAG – IEEE 1149.1 compliant. The modules outside are accessed by the processor core using AHBL or Local Bus Interface.

​The Lattice Semiconductor DDR3 Memory Controller IP Core provides a solution to interface with DDR3 SDRAM. Lattice provides a turnkey solution consisting of a controller, DDR PHY, and associated clocking and training logic. The DDR3 Memory Controller IP Core reduces the effort required to integrate a memory controller with user application designs. It minimizes the need to directly handle the DDR3 SDRAM signals by providing AXI4 interface support.​

  • DDR3 Memory Controller features support for Nexus
  • Compliance with AMBA AXI4 and AMBA AHB Protocol
  • Memory Controller supports DDR3, compliant to JESD79-3C DDR3 SDRAM standard
  • Support 7-Segement LEDs demo as application software that runs on DDR3 SDRAM
  • Support for AHB-Lite to AXI4 bus standard for RISC-V MC CPU instruction and data port

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