GPIO IP Core

Control for Memory Mapped or APB IO

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General Purpose Input/Output (GPIO) peripheral Soft IP is a simple IP designed to control GPIOs via Lattice Memory Mapped Interface (LMMI) or Advanced Peripheral Bus Interface (APB). When configured as an input, it can detect the state of a GPIO by reading the state of the associated register. When configured as an output, it takes the value written into the associated register and control the state of the controlled GPIO.

The IP can be attached to a CPU bus or used in bridges/peripherals needing memory organization of the I/O. The IP generator is configurable based on the number of GPIOs for a flexible use of the GPIO ports.

With APB to LMMI Optional Bridge - When APB is selected as the interface from the user interface, the APB to LMMI bridge is instantiated and the LMMI is replaced by APB interface. This optional bridge is implemented to interface the GPIO IP in an APB system while preserving the internal LMMI for writing and reading to internal registers.

Independently Configurable Input and Output Port - Each Input and Output Port is independently configurable. Each Input Port bit can be programmed to enable interrupt on the Input Edge (Rising or Falling) or on the Level (High or Low). Each Output Port's default value can be configured from the user interface to take either 0 or 1 at the time of GPIO generation.

Features

  • Setting or clearing an output through separate registers to allow parallel control of the output
  • Setting or clearing an output through a single register
  • Separate input and output data and control registers
  • Output register reflects the output driven status
  • Input register reflects the input status

Block Diagram

GPIO Block DiagramExpand Image

GPIO Top Level Block Diagram

Resource Utilization

Nexus Family
LIFCL-40-9BG400I
Configuration Clk Fmax (MHz)* Registers LUTs DSP
Default 200 11 34 0
Number of I/O Lines is 32 200 361 345 0
Number of I/O Lines is 32, and Remove Tri-State Buffer is enabled 200 361 374 0

*Note: Fmax is generated when the FPGA design only contains GPIO IP Core and the target Frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design

LFD2NX-40-9BG2561I
Configuration Clk Fmax (MHz)* Registers LUTs EBRs
Default 200 20 35 0
Weighted Round robin 200 361 345 0
Number of I/O Lines is 32, and Remove Tri-State Buffer is enabled 200 361 374 0

*Note: Fmax is generated when the FPGA design only contains GPIO IP Core and the target Frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design.

LFCPNX-100-9LFG672I
Configuration Clk Fmax (MHz)* Registers LUTs EBRs
Default 200 20 35 0
Weighted Round robin 200 361 345 0
Number of I/O Lines is 32, and Remove Tri-State Buffer is enabled 200 361 374 0

*Note: Fmax is generated when the FPGA design only contains GPIO IP Core and the target Frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design.

Ordering Information

Available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
Downloads
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
GPIO IP Core - Lattice Radiant Software
FPGA-IPUG-02076 2.2 3/8/2023 PDF 574.2 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
GPIO IP Core
1.0 3/31/2018 IPK 86.4 KB
GPIO IP Core User Guide
1.0 2/21/2018 PDF 709.1 KB

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