通用输入/输出（GPIO）外设IP旨在通过莱迪思存储器映射接口（LMMI）或高级外设总线接口（APB）来控制GPIO。配置为输入端口时，它可以通过读取相关寄存器的状态来检测某一GPIO的状态。配置为输出端口时，它取出写入相关寄存器的值并控制受控GPIO的状态。
该IP可以连接到CPU总线，也可以在需要I/O内存组织的桥接/外围设备中使用。IP生成器可根据GPIO的数量进行配置，以灵活使用GPIO端口。
*Note: Fmax is generated when the FPGA design only contains GPIO IP Core and the target Frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design
*Note: Fmax is generated when the FPGA design only contains GPIO IP Core and the target Frequency is 100 MHz. These values may be reduced when user logic is added to the FPGA design.
Available for free to use in Lattice Radiant design software.