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    Family
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  • ECP3 : How long does it take for the SerDes TX PLL to lock?
    81
    LatticeECP3
    Architecture
    SERDES/PCS
  • What do I do with VCCIBx connection of the SERDES channel in TX only mode?
    82
    LatticeECP3
    Architecture
    SERDES/PCS
  • What are the pin location requirements when using an input clock to capture input data?
    202
    All FPGA
    Customer Board Design
    Layout Review
  • How to solve the issue of "ispVM System  doesn't detect  parallel port ISP Download Cable" ?
    209
    All FPGA
    Device Programming
    ispVM System
  • ispLEVER: Why does the I/O vector editor in the Device Information window "Expand Option" not…
    2002
    All Devices
    Device Programming
    ispVM System
  • LatticeECP3:  How do I select between the two Vol Max values 0.4V, or 0.2V documented in…
    2005
    All FPGA
    Architecture
    IO
  • All FPGA: What is the initial logic level of a register after power-up?
    204
    All FPGA
    Architecture
    General Logic
  • LatticeECP3:  We are seeing the primary clock delay to multiple IO Logic elements are the same in…
    2003
    LatticeECP3
    Architecture
    IO
  • MachXO2:Which IBIS models should I use for the MachXO2 JTAG signal pins?
    2008
    MachXO2
    Device Modeling
    IBIS
  • MachXO:Which IBIS models should I use for the MachXO JTAG signal pins?
    2009
    MachXO
    Device Modeling
    IBIS
  • Will open drain and HVOUT outputs have defined state when VCCD/VCCA are unavailable and VCCINP is…
    2020
    Power Manager II
    Inquiries
    Datasheet
  • All Devices:  Do Lattice XAUI PCS solutions only allow Ethernet frame sizes between 64 and 1518…
    2022
    All FPGA
    Architecture
    SERDES/PCS
  • LatticeECP3:  How do I determine the delay of a LaticeECP3 DCS cell from a Place and Route TRACE…
    2024
    LatticeECP3
    Architecture
    PLL/DLL/Clock Routing
  • What are the required locations for the 7:1 LVDS pins on the LatticeXP2, LatticeECP2/M or…
    203
    All FPGA
    Customer Board Design
    Layout Review
  • Diamond: How do user get a reasonable I/O timing report when PLL phase shift is very large?
    200
    All FPGA
    Implementation
    Timing Analysis
  • LatticeECP3: Should I run gate level simulations for the Peripheral Component Interconnect Express…
    2076
    LatticeECP3
    Lattice IP/Reference Design
    PCIe
  • LatticeECP3: Can the default BSDL file provided on the Lattice website be used to test a programmed…
    2077
    LatticeECP3
    Architecture
    JTAG
  • What is the optimum PCB solder mask opening and pad diameter for a Lattice package?
    2072
    All Devices
    Customer Board Design
    Layout
  • Diamond: Is there a limitation to the name that user can give for their project directory?
    2073
    All Devices
    Implementation
    Project Navigator
  • Power Manager II: What is the POR state of I2C controlled input and output pins in POWR1014A?
    2070
    Power Manager II
    Architecture
    IO
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