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  • MachXO2:Which IBIS models should I use for the MachXO2 JTAG signal pins?
    2008
    MachXO2
    Device Modeling
    IBIS
  • LatticeECP3:  We are seeing the primary clock delay to multiple IO Logic elements are the same in…
    2003
    LatticeECP3
    Architecture
    IO
  • MachXO:Which IBIS models should I use for the MachXO JTAG signal pins?
    2009
    MachXO
    Device Modeling
    IBIS
  • Will open drain and HVOUT outputs have defined state when VCCD/VCCA are unavailable and VCCINP is…
    2020
    Power Manager II
    Inquiries
    Datasheet
  • All Devices:  Do Lattice XAUI PCS solutions only allow Ethernet frame sizes between 64 and 1518…
    2022
    All FPGA
    Architecture
    SERDES/PCS
  • LatticeECP3:  How do I determine the delay of a LaticeECP3 DCS cell from a Place and Route TRACE…
    2024
    LatticeECP3
    Architecture
    PLL/DLL/Clock Routing
  • LatticeECP3: Should I run gate level simulations for the Peripheral Component Interconnect Express…
    2076
    LatticeECP3
    Lattice IP/Reference Design
    PCIe
  • LatticeECP3: Can the default BSDL file provided on the Lattice website be used to test a programmed…
    2077
    LatticeECP3
    Architecture
    JTAG
  • What is the optimum PCB solder mask opening and pad diameter for a Lattice package?
    2072
    All Devices
    Customer Board Design
    Layout
  • Diamond: Is there a limitation to the name that user can give for their project directory?
    2073
    All Devices
    Implementation
    Project Navigator
  • Power Manager II: What is the POR state of I2C controlled input and output pins in POWR1014A?
    2070
    Power Manager II
    Architecture
    IO
  • Why is the error "Unable to locate valid JED file" generated when compiling in PAC-Designer?
    2064
    Platform Manager
    PAC-Designer
    Compile/Fit
  • LatticeECP3: How does the Big/Little Endian switch mode affects the functionality of the FIFO DC?
    2095
    All FPGA
    Architecture
    Memory EBR/Distributed
  • LatticeECP3: What is the usage of WB_CTI_I signal in the Lattice PCI Express Scatter Gather DMA Demo…
    2069
    LatticeECP3
    Lattice IP/Reference Design
    PCIe
  • LatticeECP3: Is it allowable to bypass the PCS 8B10B encoding/decoding function and still use the…
    2099
    All FPGA
    Architecture
    SERDES/PCS
  • Power Manager 2: Does it allow to read a 1.0 Volt signal from the ADC with attenuator setting 1…
    2093
    Power Manager II
    Architecture
    I2C
  • LatticeECP3/SGMII: Does the different number of preambles (5 or 6) on the Lattice SGMII IP (Serial…
    2097
    LatticeECP3
    Lattice IP/Reference Design
    SGMII
  • How many HDL sub modules can I import in a Platform Manager design using PAC software ?
    2050
    Platform Manager
    PAC-Designer
    LogiBuilder
  • LatticeECP3 datasheet shows that LVDS (Low Voltage Differential Signal) output buffer can run at…
    2018
    LatticeECP3
    Architecture
    Generic DDR
  • When executing multiple Place and Route (PAR) Jobs in parallel, what is the maximum number that can…
    2011
    All FPGA
    Implementation
    PAR
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