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    ID
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  • What can I do to maximize the emulated LVDS data rate?
    843
    All FPGA
    Architecture
    IO
  • Should I add a series inductor between my voltage regulator output and VCC core?
    848
    All Devices
    Power
  • My design includes mature devices, how long will they be available?
    845
    All Devices
    Inquiries
    PCN
  • My original design used GAL "A" devices, do I need to change my design to use the "D" devices?
    842
    GAL/ispGAL
    Architecture
    Configuration/Programming
  • When running a design using AIL, such as a SPI4.2 design, in ispLEVER using an LatticeSC/M device,…
    131
    LatticeSC/M
    Architecture
    IO
  • My PC died, can I get a replacement license for my new PC?
    861
    All Devices
    Licensing
    ispLEVER
  • Lattice Diamond: Where can I find information on the clock domains in my design?
    132
    All FPGA
    Implementation
    Timing Analysis
  • ECP3 : How long does it take for the SerDes TX PLL to lock?
    81
    LatticeECP3
    Architecture
    SERDES/PCS
  • Diamond: How can user block clock domain transfers where there is already synchronizer circuits in…
    134
    All FPGA
    Implementation
    Timing Analysis
  • Lattice Diamond: ECP2M: PCS: How can I control the location of an LatticeECP2M PCS block?
    833
    LatticeECP2/M
    Implementation
    Design Planner
  • PAC-Designer: What is the best way to get started on using Lattice PAC-Designer Mixed Signal…
    830
    All Power Management
    PAC-Designer
    LogiBuilder
  • PAC-Designer: How do I convert my Logi-Builder design code to ABEL?
    831
    All Power Management
    PAC-Designer
    ABEL
  • Power Manager II: How to implement multiple POWR1220AT8 Power Manager devices on a board?
    832
    Power Manager II
    Customer Board Design
    Schematic
  • Internal Reference: How to  implement a clock redundancy MUX with a Dynamic Clock Selection MUX…
    135
    All FPGA
    Architecture
    PLL/DLL/Clock Routing
  • Power Manager II: What is the maximum junction temperature Tj for the POWR1220AT8 device?
    800
    Power Manager II
    Reliability and Materials
    Device Materials
  • Power Manager II: What is the Peak Reflow Temperature for the ProcessorPM or POWR605?
    801
    Power Manager II
    Reliability and Materials
    Device Materials
  • Power Manager II: How to read the value of NODES in the PAC-POWR1220AT8 via I2C?
    804
    Power Manager II
    Fabric
    Schematic
  • How can the default/recent projects (.xcf) be cleared in the File menu of ispVM?
    1318
    All Devices
  • ispLEVER: What is the "Repetitive Download" tool in ispVM System software used for?
    1319
    All Devices
    Device Programming
    ispVM System
  • Can the PCI Master/Target IP core operate as a stand-alone Bus Master?
    1316
    All Devices
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