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  • Lattice Diamond: How do I interpret the Signal/Pad report Pin Info such as: "unused PULL:DOWN"? 
    6522
    All FPGA
    Implementation
    Constraint-Pref Editor
  • All Nexus: For Nexus SED/SEC, is 1-bit of error always correctable?
    6583
    CertusPro-NX
    Processor, Controller & Peripheral
  • Nexus Devices: Where to find the information of the I3C Common Command Code (CCC) for Nexus…
    6581
    CertusPro-NX
    Architecture
    Configuration/Programming
  • Radiant 3.1: How to acquire clock skew report on Nexus devices for same source and destination…
    6580
    CertusPro-NX
    Implementation
    Timing Analysis
  • What are the steps to compile/elaborate a SERDES based design in NC-Verilog?
    2165
    LatticeECP3
    Simulation
    NC-Verilog
  • ECP3: Can output enable signal be used for 7:1 LVDS design?
    2676
    LatticeECP3
    Architecture
    IO
  • PAC Designer: In Trim Configuration Options, what does "Open External Resistors(s) Threshold"…
    2674
    Power Manager II
    Customer Board Design
    Schematic Review
  • Does Lattice recommend special handling of the CSSPIN pin for FPGA's configured via master SPI…
    2677
    All FPGA
    Device Programming
    Configuration/Programming
  • How can I run ispLEVER tools on Windows 7 32-bit versions?
    1030
    All Devices
    Installation
    Win 7
  • Are there any limitations with ispLEVER Starter and service packs?
    1039
    All Devices
    Licensing
    ispLEVER
  • LatticeMico32: Why does my LatticeMico32 debug session fail to launch?
    1037
    All FPGA
    Lattice IP/Reference Design
    LatticeMico32
  • Can I run ispLEVER in 64-bit Windows 7 or 64-bit Windows Vista?
    1031
    All Devices
    Installation
    ispVM System-Win 7
  • Do the unused I/O pins need to be grounded in a device?
    1033
    All Devices
    Architecture
    IO
  • How to set LatticeECP3 FPGA IO in temporary tri-state when another partner device in line card…
    1052
    LatticeECP3
    Architecture
    IO
  • Aldec: How can user check if the license for Aldec Active-HDL is available?
    1053
    All Devices
    Other
  • [iCE40 LP/HX] Does iCE40 supports implementation of 7:1 LVDS display interface?
    4207
    iCE40
    Lattice IP/Reference Design
    7:1 LVDS Video
  • Can I use a USB to parallel port adapter with my parallel port ispDOWNLOAD cable?
    1040
    All Devices
    Device Programming
    Cables
  • How do I instantiate multiple Reveal cores into a design?
    1047
    All FPGA
    Debugging
    Reveal
  • How do I manually update ispLEVER and Diamond software?
    1043
    All Devices
    Installation
    Win-All
  • ECP5: How does the SPI (Serial Peripheral Interface) write the data into SPI Flash and what is the…
    4291
    All FPGA
    Device Programming
    Configuration/Programming
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