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  • User Background Blurring Demonstration

    Demo

    User Background Blurring Demonstration

    Efficient and low power approach for implementing user background blurring using Lattice CrossLink-NX FPGA
    User Background Blurring Demonstration
  • Scene Segmentation Reference Design

    Reference Design

    Scene Segmentation Reference Design

    Efficient and low power approach for implementing scene segmentation using Lattice CrossLink-NX FPGA
    Scene Segmentation Reference Design
  • Object Counting AI

    Reference Design

    Object Counting AI

    An example object counting application based on the Lattice sensAI stack. Includes SPI, DDR IP blocks, ISP engine, 8 CNN engines and a counting / overlay engine
    Object Counting AI
  • Human Counting AI Demo

    Demo

    Human Counting AI Demo

    Human upper-body detection and counting demonstration utilizes Lattice’s ECP5 FPGA and a Convolutional Neural Network (CNN) acceleration engine
    Human Counting AI Demo
  • Ikva ML Accelerator IP Core

    IP Core

    Ikva ML Accelerator IP Core

    Powerful, scalable ML accelerator supporting 8-bit CNNs and 1-bit Binarized Neural Networks (BNNs), a rich software stack and computer vision models.
    Ikva ML Accelerator IP Core
  • DCA1000 Evaluation Module

    Board

    DCA1000 Evaluation Module

    The DCA1000EVM receives LVDS-format radar-sensing data and can stream over Ethernet in real-time. The board also connects to TI’s 77GHz xWR1xxx EVM.
    DCA1000 Evaluation Module
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