PCI Express x1 & x4 IP Core for Nexus-based FPGAs

Easy-to-use Transaction Layer Interface to the PCI Express Bus

PCI Express is a high performance, fully scalable, well-defined standard for a wide variety of computing and communications platforms. Being a packet based serial technology, PCI Express greatly reduces the number of required pins and simplifies board routing and manufacturing. PCI Express is a point-to-point technology, as opposed to the multi-drop bus in PCI. Each PCI Express device has the advantage of full duplex communication with its link partner to greatly increase overall system bandwidth. The basic data rate for a single lane is double that of the 32 bit/33 MHz PCI bus. A four-lane link has eight times the data rate in each direction of a conventional bus.

The Lattice PCIe X1 & X4 Cores provide a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express® Bus. The Lattice PCIe X1 & X4 Cores implementation is a hardened IP with soft logic provided for interface conversion options. The hardened IP is an integration of PHY and Link Layer blocks from third party vendors.

Features

  • PCIe X1 core is compliant with PCI Express Base Specification Revision 3.0 and supports 5.0 GT/s, and 2.5 GT/s line rates
  • PCIe X4 core is compliant with PCI Express Base Specification Revision 4.0 and supports 8.0GT/s, 5.0 GT/s, and 2.5 GT/s line rates
    • With built in DMA capability and AXI interface
  • Comprehensive application support with both Endpoint and Root port configurations
  • Multi-Function support with 1-4 Physical Functions per Link
  • Implements all 3 PCI Express Layers (Transaction, Data Link, Physical)
    * The Lattice PCIe X1 IP Core is supported in CrossLink™-NX and Certus™-NX FPGA device families, and PCIe X4 IP Core is supported in CertusPro™-NX FPGA device family

Jump to

Block Diagram

Performance and Size

PCI Express IP Configuration

x1 Native X1 Native X2 Native X4 Native
FPGA Families Supported CrossLink-NX Certus-NX CertusPro-NX CertusPro-NX CertusPro-NX
Targeted Device LIFCL-40 LFD2NX-40 LFCPNX-100 LFCPNX-100 LFCPNX-100
Data Path Width (Core Data Width)
32 32 32 64 128
PCI Express Link Speed
Gen2 (2.5 & 5.0 GT/s) Gen2 (2.5 & 5.0 GT/s)
Gen3 (2.5, 5.0 & 8.0 GT/s)
Data Path Width (Core Data Width)
- 1x4, 1x2, 1x1, 1x2+1x1, 2x1
LUTs 5217 5217 TBD
sysMEMTM EBRs 29 29
Registers 3172 3172

Ordering Information

Device Family Partner Number
Single Design Multi-Site Subscription
CertusPro-NX PCI-EXP1-CPNX-U PCI-EXP1-CPNM-UT PCI-EXP1-CPNX-US
PCI-EXP2-CPNX-U PCI-EXP2-CPNM-UT PCI-EXP2-CPNX-US
PCI-EXP4-CPNX-U PCI-EXP4-CPNM-UT PCI-EXP4-CPNX-US
PCI-ERC1-CPNX-U PCI-ERC1-CPNM-UT PCI-ERC1-CPNX-US
PCI-ERC2-CPNX-U PCI-ERC2-CPNM-UT PCI-ERC2-CPNX-US
PCI-ERC4-CPNX-U PCI-ERC4-CPNM-UT PCI-ERC4-CPNX-US
CrossLink-NX PCI-EXP1-CNX-U PCI-EXP1-CNX-UT PCI-EXP1-CNX-US
Certus-NX PCI-EXP1-CTNX-U PCI-EXP1-CTNX-UT PCI-EXP1-CNTX-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the PCI Express Endpoint IP core, please contact your local Lattice Sales Office.

PCIe Solutions for Nexus FPGAs

PCIe Basic Demo on Crosslink-NX PCIe Bridge Board

Demo

PCIe Basic Demo on Crosslink-NX PCIe Bridge Board

The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
PCIe Basic Demo on Crosslink-NX PCIe Bridge Board
PCIe Colorbar Demo for Lattice Nexus-based FPGAs

Demo

PCIe Colorbar Demo for Lattice Nexus-based FPGAs

Demo that displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
PCIe Colorbar Demo for Lattice Nexus-based FPGAs
PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

Demo

PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
PCIe Multifunction Demo for Lattice Nexus-based FPGAs

Demo

PCIe Multifunction Demo for Lattice Nexus-based FPGAs

Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
PCIe Multifunction Demo for Lattice Nexus-based FPGAs
Lattice mVision MIPI Video Sensor to PCIe Bridge Demonstration

Demo

Lattice mVision MIPI Video Sensor to PCIe Bridge Demonstration

This design demonstrates the functionality of transferring MIPI CSI-2 sensor video data to a computer through PCIe with a Direct Memory Access (DMA) engine.
Lattice mVision MIPI Video Sensor to PCIe Bridge Demonstration

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
PCIE X4 IP Core - Lattice Radiant Sofware
FPGA-IPUG-02126 1.0 6/23/2021 PDF 3.6 MB
PCIe Endpoint IP Core - Lattice Radiant Software
FPGA-IPUG-02091 1.4 10/4/2021 PDF 4.4 MB
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