PCI Express for Nexus FPGAs

Easy-to-use Transaction Layer Interface to the PCI Express Bus

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PCI Express® is a high performance, fully scalable, and well-defined standard for a wide variety of computing and communications platforms. As a packet-based serial technology, the PCI Express standard greatly reduces the number of required pins and simplifies board routing and manufacturing.

With Lattice Nexus platform, Lattice offers x1 and up to x4 lanes. Both provide a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus. The implementation is a hardened IP with soft logic provided for interface conversion options. The hardened IP is an integration of PHY and Link Layer blocks.

Lattice PCIe x1 IP Core is supported in the CrossLink™-NX and Certus™-NX FPGA device families and is available in the Lattice Radiant™ software.

Lattice PCIe X4 IP Core is supported in the CertusPro-NX™ and MachXO5™-NX FPGA device families and is available in the Lattice Radiant™ software.

Latest Resource Utilization details are available in the PCIe X1 IP Core and PCIE X4 IP Core User Guides.

Features

Hard IP PHY

PCIE x1

  • PCI Express Base Specification Revision 3.0 compliant, including compliance with earlier PCI Express Specifications
  • Backward compatible with PCI Express 2.x, and 1.x
  • x1 PCI Express Lane only
  • 5.0 GT/s, and 2.5 GT/s line rate support

PCIE x4

  • PCI Express Base Specification Revision 4.0 compliant, including compliance with earlier PCI Express Specifications
  • Backward compatible with PCI Express 3.x, 2.x, and 1.x
  • X4 PCI Express Lanes with bifurcation options such as 1×4, 1×2, 1×1, 1×2+1×1, and 2×1 lane configurations
  • 8.0GT/s, 5.0 GT/s, and 2.5 GT/s line rate support

Soft IP Key Features for both x1 and x4 Lanes

  • AHB-Lite Data Interface Option with DMA and Non-DMA support
  • AXI4-Stream Data Interface Option
  • APB Register Interface

Jump to

Block Diagram

PCI Express x1 & x4 IP Core for Nexus-based FPGAsExpand Image
  • PCIe x1 IP Core Block Diagram for CrossLink-NX, Certus-NX
  • The Lattice PCIe x1 IP Core implements all three layers defined by the PCI Express Specification
  • The soft logic is provided for optional interface conversion such as:
    AHB-Lite, AXI4-Stream, and APB for registers access
PCI Express x1 & x4 IP Core for Nexus-based FPGAsExpand Image
  • PCIe X4 IP Core Block Diagram for CertusPro-NX and MachXO5-NX
  • The Lattice PCIe X4 IP Core implements all three layers defined by the PCI Express Specification
  • The soft logic is provided for optional interface conversion such as:
    Non-DMA AHB-Lite (supported in IP versions older than 3.0.0), Non-DMA AXI4-Stream, and APB fore register accesses

Performance and Size

PCI Express IP Configuration

x1 Native X1 Native X2 Native X4 Native X1 Native
FPGA Families Supported CrossLink-NX Certus-NX CertusPro-NX CertusPro-NX CertusPro-NX MachXO5-NX
Targeted Device LIFCL-40 LFD2NX-40 LFCPNX-100 LFCPNX-100 LFCPNX-100 LFMXO5-55T
Data Path Width (Core Data Width)
 32 32 32 64 128 32
PCI Express Link Speed Gen2 (2.5 & 5.0 GT/s) Gen2 (2.5 & 5.0 GT/s) Gen2 (2.5 & 5.0 GT/s)
Gen3 (2.5, 5.0 & 8.0 GT/s)
Data Path Width (Core Data Width)
 - - 1x4, 1x2, 1x1, 1x2+1x1, 2x1 1x1
LUTs 5217 5217 4070 5723 8966 4070
sysMEMTM EBRs 29 29 9 15 28 9
Registers 3172 3172 2576 3640 6102 2576

Ordering Information

The following table details the distinctions among Lattice Nexus FPGA devices, emphasizing key aspects such as targeted device, data path width, link speed, and LUTs.

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
CertusPro-NX PCI-EXP4-CPNX-UT
PCI-EXP2-CPNX-UT
PCI-EXP1-CPNX-UT		 PCI-EXP4-CPNX-US
PCI-EXP2-CPNX-US
PCI-EXP1-CPNX-US
MachXO5-NX PCI-EXP1-XO5-UT PCI-EXP1-XO5-US
CrossLink-NX PCI-EXP1-CNX-UT PCI-EXP1-CNX-US
Certus-NX PCI-EXP1-CTNX-UT PCI-EXP1-CTNX-US

OPN Reference Guide

PCI-EXP4: covers x1, x2 and x4
PCI-EXP2: covers x1 and x2

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the PCI Express Endpoint IP core, please contact your local Lattice Sales Office.

PCIe Solutions for Nexus FPGAs

PCIe Basic Demo for Lattice Nexus-based FPGAs

Demo

PCIe Basic Demo for Lattice Nexus-based FPGAs

The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
CrossLink-NX, Certus-NX, CertusPro-NX 
SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Defense, LED, Nexus PCIe 
PCIe Basic Demo for Lattice Nexus-based FPGAs
PCIe Colorbar Demo for Lattice Nexus-based FPGAs

Demo

PCIe Colorbar Demo for Lattice Nexus-based FPGAs

PCIe Colorbar Demo displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
CrossLink-NX, Certus-NX, CertusPro-NX 
SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Defense, LED, Nexus PCIe 
PCIe Colorbar Demo for Lattice Nexus-based FPGAs
PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

Demo

PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
CrossLink-NX, Certus-NX, CertusPro-NX 
SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Defense, LED, Nexus PCIe 
PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
PCIe Multifunction Demo for Lattice Nexus-based FPGAs

Demo

PCIe Multifunction Demo for Lattice Nexus-based FPGAs

Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 
SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Defense, I2C, LED, GPIO, Nexus PCIe 
PCIe Multifunction Demo for Lattice Nexus-based FPGAs
Lattice mVision MIPI Video Sensor to PCIe Bridge Demonstration

Demo

Lattice mVision MIPI Video Sensor to PCIe Bridge Demonstration

This design demonstrates the functionality of transferring MIPI CSI-2 sensor video data to a computer through PCIe with a Direct Memory Access (DMA) engine.
CertusPro-NX 
Lattice mVision, MIPI, CSI-2, DMA, PCIe, Nexus PCIe 
Lattice mVision MIPI Video Sensor to PCIe Bridge Demonstration
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Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
PCIe x1 IP Core User Guide
FPGA-IPUG-02091 1.9 12/20/2024 PDF 4.5 MB
PCIe x4 IP Core User Guide
FPGA-IPUG-02126 1.8 12/20/2024 PDF 8.4 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
PCIe x4 IP Release Notes
FPGA-RN-02059 1.0 12/20/2024 PDF 211 KB
PCIe x1 IP Release Notes
FPGA-RN-02060 1.0 12/20/2024 PDF 207.5 KB

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