PCI Express for Nexus FPGAs

Easy-to-use Transaction Layer Interface to the PCI Express Bus

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PCI Express® is a high performance, fully scalable, and well-defined standard for a wide variety of computing and communications platforms. As a packet-based serial technology, the PCI Express standard greatly reduces the number of required pins and simplifies board routing and manufacturing.

With Lattice Nexus platform, Lattice offers x1 and up to x4 lanes. Both provide a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus. The implementation is a hardened IP with soft logic provided for interface conversion options. The hardened IP is an integration of PHY and Link Layer blocks.

Lattice PCIe x1 IP Core is supported in the CrossLink-NX, Certus-NX, MachXO5-NX FPGA device families and is available in the Lattice Radiant™ software.

Lattice PCIe x4 IP Core is supported in the CertusPro-NX™ and MachXO5™-NX1 FPGA device families and is available in the Lattice Radiant™ software.

Note: 1. MachXO5-NX is configurable to x1.

Latest Resource Utilization details are available in the PCIe X1 IP Core and PCIE X4 IP Core User Guides.

Features

Hard IP PHY

PCIE x1

  • Transmitter: Configurable driver impedance, amplitude. Support for one lane
  • Receiver: Configurable receiver impedance, Continuous Time Linear Equalizer (CTLE) gain, 1-Tap Decision Feedback.
  • PCS: Rate negotiation support. Selectable parallel data widths such as 5, 10, and 16
  • Link Layer:
    • PCI Express Base Specification Revision 3.0 compliant, including compliance with earlier PCI Express Specifications.
    • Backward compatible with PCI Express 2.x, and 1.x
    • x1 PCI Express Lane only
    • 5.0 GT/s, and 2.5 GT/s line rate support

PCIE x4

  • Transmitter: Configurable driver impedance, amplitude, and 3-tap pre-emphasis. Support for four lanes
  • Receiver: Configurable receiver impedance, Continuous Time Linear Equalizer (CTLE) gain, 1-Tap Decision Feedback Equalization (DFE), and support for equalizer adaptation.
  • PCS: Rate negotiation support. Selectable parallel data widths such as 5, 10, and 16
  • Link Layer:
    • PCI Express Base Specification Revision 4.0 compliant, including compliance with earlier PCI Express Specifications
    • Backward compatible with PCI Express 3.x, 2.x, and 1.x
    • X4 PCI Express Lanes with bifurcation options such as 1×4, 1×2, and 1×1 lane configurations
    • 8.0GT/s, 5.0 GT/s, and 2.5 GT/s line rate support

Jump to

Block Diagram

PCIe_x1Expand Image
  • PCIe x1 IP Core Block Diagram for CrossLink-NX, Certus-NX
  • The Lattice PCIe x1 IP Core implements all three layers defined by the PCI Express Specification
  • The soft logic is provided for optional interface conversion such as:
    AHB-Lite, AXI4-Stream, and APB for registers access
PCIe X4 IP Core Block DiagramExpand Image
  • PCIe X4 IP Core Block Diagram for CertusPro-NX and MachXO5-NX
  • The Lattice PCIe X4 IP Core implements all three layers defined by the PCI Express Specification
  • The soft logic is provided for optional interface conversion such as:
    Non-DMA AHB-Lite (supported in IP versions older than 3.0.0), Non-DMA AXI4-Stream, and APB fore register accesses

Performance and Size

PCI Express IP Configuration
PCIe IP PCIE_X1 PCIE_X4
X1 Native X1 Native X1 Native X1 Native X1 Native X2 Native X4 Native
FPGA Families Supported CrossLink-NX Certus-NX MachXO5-NX MachXO5-NX CertusPro-NX CertusPro-NX CertusPro-NX
Targeted Device LIFCL-40 LFD2NX-40 LFMXO5-35T
LFMXO5-65T		 LFMXO5-55T,
LFMXO5-100T,
LFMXO5-55TD,
LFMXO5-55TDQ		 LFCPNX-100 LFCPNX-100 LFCPNX-100
Data Path Width (Core Data Width)
 32 32 32 32 32 64 128
PCI Express Link Speed Gen2 (5.0 GT/s)
Gen1 (2.5 GT/s)		 Gen2 (5.0 GT/s)
Gen1 (2.5 GT/s)		 Gen3 (8.0 GT/s)
Gen2 (5.0 GT/s)
Gen1 (2.5 GT/s)
Data Path Width (Core Data Width) 1x1 1x1 1x1 1x1 1x4, 1x2, 1x1
LUTs 303 303 303 326 326 399 544
sysMEMTM EBRs 0 0 0 0 0 0 0
Registers 0 0 0 3 3 3 3

Ordering Information

The PCIe x1 and x4 IP are available with the Lattice Radiant Subscription software. To purchase the Lattice Radiant Subscription license, contact
Lattice Sales or go to the Lattice Online Store.

PCIe Solutions for Nexus FPGAs

PCIe Basic Demo for Lattice Nexus-based FPGAs Block Diagram

Demo

PCIe Basic Demo for Lattice Nexus-based FPGAs

The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
CrossLink-NX, Certus-NX, CertusPro-NX 
SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Defense, LED, Nexus PCIe 
PCIe Basic Demo for Lattice Nexus-based FPGAs
PCIe Colorbar Demo on Crosslink-NX PCIe Bridge Board - Block Diagram

Demo

PCIe Colorbar Demo for Lattice Nexus-based FPGAs

PCIe Colorbar Demo displays a series of moving colorbars by streaming the image data using DMA transfers from the FPGA to the host system.
CrossLink-NX, Certus-NX, CertusPro-NX 
SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Defense, LED, Nexus PCIe 
PCIe Colorbar Demo for Lattice Nexus-based FPGAs
PCIe DMA Throughput Demo on Crosslink-NX PCIe Bridge Board - Block Diagram

Demo

PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs

The PCI Express DMA Throughput Demo allows to initiate DMA read and write transactions, transferring data from the host to the FPGA and vice versa.
CrossLink-NX, Certus-NX, CertusPro-NX 
SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Defense, LED, Nexus PCIe 
PCIe DMA Throughput Demo for Lattice Nexus-based FPGAs
PCIe Multifunction Demo on Crosslink-NX PCIe Bridge Board - Block Diagram

Demo

PCIe Multifunction Demo for Lattice Nexus-based FPGAs

Demonstrates the multifunction capabilities of the Crosslink-NX FPGA that allows access to GPIO, MDIO and I2C registers.
CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 
SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Defense, I2C, LED, GPIO, Nexus PCIe 
PCIe Multifunction Demo for Lattice Nexus-based FPGAs
MIPI CSI-2 to PCIe Reference Design

Reference Design

MIPI CSI-2 to PCIe Reference Design

CertusPro™‑NX MIPI CSI‑2 to PCIe reference design streams camera video to a PC via DMA on the Versa Board, with Linux drivers and capture‑to‑display demo.
CertusPro-NX 
CSI, FPGA, MIPI, OS, PCIe, Video Tx/Rx, AR / VR & Drones, Home Control Appliances & Security, IoT & Wearables, Notebooks & PCs, Printers, Smart Toys & Robots, Tablets, Automotive, Lattice mVision, Lattice Automate, Nexus PCIe 
MIPI CSI-2 to PCIe Reference Design
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Documentation

Quick Reference
Information Resources
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Lattice Avant and Nexus Linux PCIe Host DMA Driver User Guide
FPGA-TN-024331.07/27/2026PDF936.1 KB
Lattice Avant and Nexus Linux PCIe Host Non-DMA Driver User Guide
FPGA-TN-024241.012/11/2025PDF1.8 MB

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PCIe x1 IP Core - User Guide
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PCIe x4 IP Core - User Guide
FPGA-IPUG-021262.56/26/2026PDF8.8 MB
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PCIe x1 IP Core - Release Notes
FPGA-RN-020601.66/26/2026PDF344.6 KB
PCIe x4 IP Core - Release Notes
FPGA-RN-020591.86/26/2026PDF349.4 KB