MIPI-HDMI Reference Design is built using multiple Lattice IPs and some additional glue logic necessary to connect the IPs in a processing pipeline. The Lattice IPs included in this design are: MIPI CSI-2 Receiver, Byte to pixel, Debayer, Automatic white balance (AWB) and Color correction matrix (CCM).
The MIPI CSI-2 to HDMI Reference Design includes the synthesizable MIPI-HDMI core design and stimulus generators, checkers, and a testbench necessary to simulate the design.
MIPI CSI-2 to HDMI Reference Design – The stimulus is generated by a MIPI traffic generator (CSI-2 D-PHY Tx IP) fed by video frames created from image files. The final output is captured into multiple image files, one for each frame. The input and output files can be viewed on a computer monitor for visual equivalency checking.