​​eSPI Target IP Core​

Compliant with Intel eSPI Specs, Featuring a Dedicated Virtual Wire Channel

The Lattice Enhanced Serial Peripheral Interface (eSPI) Target IP is compliant with the Intel eSPI specifications. It has its own virtual wire channel in the user interface while implementing peripheral channels, namely, Out of Band (OOB) Message Channel and Flash Access Channel in FIFO that are accessible by the APB or AHB-Lite interface.

Resource Utilization details are available in the IP Core User Guide.​

Features

  • ​​Supports all eSPI Commands.​
  • Supports all required error detection in eSPI specification.​
  • Supports Single, Dual, and Quad SPI mode.​
  • Simple implementation interface for virtual wire channel transactions.​
  • GPIO Expander interface for virtual wire channel transactions.​

Block Diagram

Ordering Information

​​The eSPI Target IP is provided at no additional cost with the Lattice Radiant™ software.​

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
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​eSPI Target IP Core – User Guide​
FPGA-IPUG-02260 1.0 6/28/2024 PDF 1.2 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
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​eSPI Target IP Core – Release Notes​
FPGA-RN-02002 1.0 6/28/2024 PDF 180.5 KB

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