I2C to APB Bridge Reference Design

Bidirectional Interface between One I2C Master and One APB Slave

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The I2C-to-APB Bridge Reference Design is used for interfacing one I2C Master and one APB Slave. This bridge has two sections: the I2C Slave section, and the APB Master section. An external I2C Master is required to use this bridge, while the APB Slave can be implemented within the FPGA fabric. When interfacing to multiple APB Slaves, the user can use either an APB interconnect IP or multiple instantiations of this I2C to APB Bridge with different Slave addresses.

The I2C-to-APB Bridge Reference Design provides an interface between the low speed I2C Bus and the AMBA 3 APB Bus. The design is implemented in Verilog HDL and comes in .ipk format that is installed within Lattice Propel™ Builder software as an IP. Implementation is done within the Lattice Diamond® software.

Support APB Read / Write Capability – This reference design converts I2C transactions from an external I2C Master into APB Master transaction.


  • Compliance with AMBA 3 APB Protocol v1.0
  • APB Data Bus width of 32 bits
  • APB Address width of 32-bits
  • Registered output

Block Diagram

I2C to APB Bridge Reference Design Block Diagram


Technical Resources
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I2C to APB Bridge Reference Design - Source Code
3/10/2023 ZIP 223.4 KB
I2C to APB Bridge Reference Design - Documentation
FPGA-RD-02263 1.0 3/10/2023 PDF 1.5 MB

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