The System Memory is designed to be fully compatible with the AHB-Lite and AXI4 standards. It can be configured as a single or dual AHB-Lite interface, depending on if single or dual port memory is needed. The signals from the AHB-L bus are translated into memory compatible signals, which can be directly interpreted by the core memory implementation. But unlike in the AHB-Lite interface, AXI4 is always implemented as a dual port memory. One port of the memory is assigned to AXI4 Write Channels, while the other port is assigned to AXI4 Read Channels. Similar to AHB-Lite interface, AXI4 transactions are translated to memory compatible signals that are directly interpreted by the core memory.
The System Memory Module employs the use of Embedded Block RAMs or Distributed Memory in the MachXO3D family of devices. The memory implementation can be configured as true-dual port, pseudo dual port, single port, or read-only memory.
FIFO Interface - There is a dedicated FIFO interface shared with the AHB-L port S1. This interface is used to inject FIFO data from a FIFO stream.
AXI4-Stream Interface - When the set interface for System Memory is AXI4, the data streamer interface can be set to AXI4-Stream. This interface is fully compatible to the AXI4-Stream standard and is implemented to have a priority to the other AXI4 Write transactions when valid data stream is given.
Memory Implementation - The System Memory Module uses Embedded Block RAMs (EBR) or Distributed Memory in the MachXO3D family of devices, as well Large RAM for LIFCL, LFCPNX, and LFD2NX family of devices. The memory implementation can be configured as true-dual port, pseudo dual port, single port, or read-only memory.