系统存储器模块

使用嵌入式RAM块或分布式存储器

系统存储器在设计上与AHB-Lite标准完全兼容。它可以配置为单AHB-Lite或双AHB-Lite接口,取决于是否需要单端口或双端口存储器。桥接器将来自AHB-L总线的信号转换为与存储器兼容的信号,可以直接被核心存储器所解读。

系统存储器模块使用MachXO3D系列设备中的嵌入式RAM块或分布式存储器。可以将存储器配置为真双端口、伪双端口、单端口或只读。

可以使用莱迪思Propel Builder软件配置和生成IP。它可以用于MachXO3D FPGA器件,并使用集成了Synplify Pro综合工具的莱迪思Diamond布局布线工具来实现。

特性

  • 符合AMBA 3 AHB-Lite协议v1.0
  • 单或双端口存储器(连接1或2个AHB-Lite从端口)
  • 与兼容硬件一起使用时支持字节写入
  • 最大支持512 kB的存储空间
  • 使用32位数据字传输,并使用低位优先(little-endian)结构
Lattice Propel

Block Diagram

Resource Utilization

Avant Family
LAV-AT-500E-2LFG1156C
Configuration Clock Fmax (MHz) Register LUTs EBRs
INTERFACE = AXI4, PORT_COUNT = 1,
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192
181.324 303 710 8
INTERFACE = AXI4, PORT_COUNT = 2 (R/W + R/W),
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192
168.039 599 1478 8
INTERFACE = AXI4, PORT_COUNT = 2 (WO + RO),
MEMORY_TYPE = Distributed_RAM, ADDR_DEPTH = 1024,
148.434 510 5093 8
INTERFACE = AXI4, PORT_COUNT = 1,
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192,
DATA_STREAMER=1, STREAMER_INTF=AXI4 (Stream)
175.593 364 801 8
INTERFACE = AHBL, PORT_COUNT = 1
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192,
250 29 131 8
INTERFACE = AHBL, PORT_COUNT = 2 (R/W + R/W)
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192,
250 58 260 8
INTERFACE = AHBL, PORT_COUNT = 2 (WO + RO)
MEMORY_TYPE = Disributed_RAM, ADDR_DEPTH = 8192,
232.775 75 4009 8
CertusPro-NX Family
LFCPNX-100-9LFG672C
Configuration Clock Fmax (MHz) Register LUTs EBRs
INTERFACE = AXI4, PORT_COUNT = 1,
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192
155.812 296 730 16
INTERFACE = AXI4, PORT_COUNT = 2 (R/W + R/W),
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192
151.286 597 1484 16
INTERFACE = AXI4, PORT_COUNT = 2 (WO + RO),
MEMORY_TYPE = Distributed_RAM, ADDR_DEPTH = 1024
95.465 530 6589 16
INTERFACE = AXI4, PORT_COUNT = 1,
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192,
DATA_STREAMER=1, STREAMER_INTF=AXI4 (Stream)
161.865 359 673 16
INTERFACE = AHBL, PORT_COUNT = 1
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192
200 29 138 16
INTERFACE = AHBL, PORT_COUNT = 2 (W/R + W/R)
MEMORY_TYPE = EBR, ADDR_DEPTH = 8192
200 58 260 16
INTERFACE = AHBL, PORT_COUNT = 2 (WO + RO)
MEMORY_TYPE = Disributed_RAM, ADDR_DEPTH = 1024
129.988 74 5444 0

文档

快速参考
标题 编号 版本 日期 格式 文件大小
选择全部
System Memory Module - User Guide
FPGA-IPUG-02073 2.1 2/4/2024 PDF 2.7 MB