10Gb Ethernet PCS IP Core

Ethernet 10GE/10GBASE-R

Related Products

The 10 Gigabit Media Independent Interface (XGMII) connects Ethernet Media Access Controllers (MACs) and Physical Layer Devices (PHYs). This IP core implements the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) functionality following the IEEE 802.3 10G Base-R specification.

Reference Clocks - The 10 Gb Ethernet PCS IP Core provides other sources of reference clocks and can be used for dynamic switching. To use this feature, user must set the reference clock source control signals accordingly.

APB and MDIO Access Support - This IP Core instantiates MPCS Module foundation IP configured as 1-Lane 64b/66b PCS, and supports APB and MDIO access to MPCS and MMD registers.

Features

  • PCS/PMA functions defined in IEEE 802.3 10G Base-R
  • 64b/66b encoding and decoding
  • Tx phase FIFO and Rx clock compensation FIFO
  • XGMII Interface: 64 bit, 156.25 MHz
  • Supports APB and MDIO Interfaces for MPCS and MMD register access

Jump to

Block Diagram

Resource Utilization

This table shows the resource utilization for the LFCPNX-100 using the Lattice Radiant software.
Device Slice Registers LUTs EBRs
LFCPNX-100 36 52 0

Ordering Information

Device Family Single-Design Multi-Site Subscription
CertusPro-NX ETHER-10GEBASER-CPNX-U ETHER-10GEBASER-CPNX-UT ETHER-10GEBASER-CPNX-US

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
10 Gb Ethernet PCS IP Core - User Guide
FPGA-IPUG-02163 1.5 10/8/2023 PDF 719.6 KB

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