The 10 Gigabit Media Independent Interface (XGMII) connects Ethernet Media Access Controllers (MACs) and Physical Layer Devices (PHYs). This IP core implements the Physical Coding Sublayer (PCS) and Physical Medium Attachment (PMA) functionality following the IEEE 802.3 10G Base-R specification.
Reference Clocks - The 10 Gb Ethernet PCS IP Core provides other sources of reference clocks and can be used for dynamic switching. To use this feature, user must set the reference clock source control signals accordingly.
APB and MDIO Access Support - This IP Core instantiates MPCS Module foundation IP configured as 1-Lane 64b/66b PCS, and supports APB and MDIO access to MPCS and MMD registers.