25Gb Ethernet MAC+PHY IP Core

Ethernet Transmission of Data Frame Compliant to the IEEE 802.3-2012 Standard

Related Products

The Lattice Semiconductor 25G Ethernet (GbE) IP core supports the ability to transmit and receive data between a host processor and an Ethernet network. The 25GbE IP core consists of a standalone 25G Ethernet PCS IP, standalone 25G Ethernet MAC IP, or a combined 25G PCS & MAC following the IEEE 802.3 25G BASE-R specification.

This IP Core is supported in the Lattice Avant-X FPGA for all available PCS and MAC options. These options are available in the Lattice Radiant™ software.

IEEE 802.3 25G BASE-R PCS/PMA Functions – Supports standard 25 Gbps Ethernet link layer data rate


  • PCS: 64b/66b encoding and decoding
  • PCS: 25GMII 128-bit wide internal data path operating at 195.3125 MHz
  • Supports AXI4L interfaces for PHY and MMD register access
  • MAC: AXI4-Stream interface for client transmit and receive
  • MAC: Supports VLAN, SVLAN, Jumbo frames, Priority flow control, pause frame control and programmable IPG

Block Diagram

Ordering Information

Device Family Part Number
Multi-site Perpetual Single Machine Annual


Quick Reference
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25G Ethernet MAC + PHY IP Core - User Guide
FPGA-IPUG-02249 2023.2 12/5/2023 PDF 1.4 MB

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