First, all the input data should be located on one side of the LatticeXP2, LatticeECP2/M, LatticeECP3 or LatticeSC/M device in order to be sampled by one edge clock. But the LatticeSC/M's bottom side is an exception. It has two banks (i.e. Bank 4, 5) each of which uses the different edge clock nets. So all the input data should be located on either Bank 4 or Bank 5 for the LatticeSC/M device. Since the LatticeECP2/M device has no IDDRs on the top side and the LatticeECP3 device has no IDDRs on the bottom side, we can not place DDR inputs on these sides.
Second, the input clock should be locked to the primary clock pin. It will directly connect to the dedicated edge clock net.
Third, if the input clock needs to go to I/O registers through a PLL, the input clock should be locked to a PLL input pin for the direct connection to the PLL.
The above considerations are to get the best margin when sampling the correct input data (especially for the high speed data rate) regardless of process, voltage and temperature (PVT) variations.