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ID: 81
Case Type: faq
Category: Architecture
Related To: SERDES/PCS
Family: LatticeECP3

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How long does it take for the SerDes TX PLL to lock?

For both LatticeECP2M and LatticeECP3, the SerDes TX PLL Lock time depends on the value of PLL_LOL_SET and the quality of the TX reference clock (REFCLK).  The times given below are measured from release of Quad Reset assuming that REFCLK is stable.

  1. PLL_LOL_SET = "00" requires 1.4 million Unit Intervals (UI)

    • 448us @ 3.125Gbps
    • 560us @ 2.5Gpbs
    • 1.12ms @ 1.25Gbps

  2. PLL_LOL_SET = "01" or "10" or "11" requires 0.7 million UI

    • 224us @ 3.125Gbps
    • 280us @ 2.5Gpbs
    • 560us @ 1.25Gbps