ECP3 : How long does it take for the SerDes TX PLL to lock?SupportArticlePageec0caa70-ac78-4d9d-9734-8b33705cad18FAQ/Support/AnswerDatabase/8/81https://edge.sitecorecloud.io/latticesemi9e32-latticesemi06bb-prod9ecc-d341/media/Project/Lattice/LatticeSemi/Images/SearchThumbnails/FAQ.png?sc_lang=enFor both LatticeECP2M and LatticeECP3, the SerDes TX PLL Lock time depends on the value of PLL_LOL_SET and the quality of the TX reference clock (REFCLK). The times given below are measured from release of Quad Reset assuming that REFCLK is stable. PLL_LOL_SET = "00" requires 1.4 million Unit Intervals (UI) 448us @ 3.125Gbps 560us @ 2.5Gpbs 1.12ms @ 1.25Gbps PLL_LOL_SET = "01" or "10" or "11" requires 0.7 million UI 224us @ 3.125Gbps 280us @ 2.5Gpbs 560us @ 1.25Gbps
