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ID: 81
实例类型: faq
分类: Architecture
相关: SERDES/PCS
产品系列: LatticeECP3

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ECP3 : How long does it take for the SerDes TX PLL to lock?

For both LatticeECP2M and LatticeECP3, the SerDes TX PLL Lock time depends on the value of PLL_LOL_SET and the quality of the TX reference clock (REFCLK). The times given below are measured from release of Quad Reset assuming that REFCLK is stable.
PLL_LOL_SET = "00" requires 1.4 million Unit Intervals (UI)

448us @ 3.125Gbps
560us @ 2.5Gpbs
1.12ms @ 1.25Gbps
PLL_LOL_SET = "01" or "10" or "11" requires 0.7 million UI

224us @ 3.125Gbps
280us @ 2.5Gpbs
560us @ 1.25Gbps