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ID: 203
Case Type: faq
Category: Customer Board Design
Related To: Layout Review
Family: All FPGA

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What are the required locations for the 7:1 LVDS pins on the LatticeXP2, LatticeECP2/M or LatticeECP3 device?

For the 7:1 LVDS pins, they will use 4:1 gear boxes in Programmable I/O Cells (PIC). Their ECLK (i.e. edge clock) and SCLK (i.e. primary clock) must have a correct timing relationship. Hence, we may use PLL or CLKDIV to generate ECLK and SCLK. 

Please note that PLL and CLKDIV are on the left or right side of the LatticeXP2, LatticeECP2/M or LatticeECP3 device. So we have to locate the 7:1 LVDS pins (TX and/or RX) on the left and/or right sides of the FPGA device in order to use the dedicated clock routing nets to guarantee the correct timing relationship.