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ID: 235
Case Type: faq
Category: Architecture
Related To: Memory EBR/Distributed
Family: All Devices

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How does the output register and read enable (RDEN) signal affect Dual Clock FIFO (FIFO_DC)?

The IPexpress tool within Lattice development software allows user to generate FIFO_DC using Embedded Block Ram (EBR) or distributed memory. During the generation of the FIFO_DC module, there are options to use output registers, and/or to use RDEN to control the output registers.


These options affect the timing of the data availability at the FIFO output during the READ operation. There are 3 scenario with and without using these options:



  1. Without using output register, the data will be available right after the clock edge that the RDEN is activated (RDEN goes high). That means data is available after Tco (Clock to Output time) of the memory. 
  2. With output register, the data will be available one clock cycle later than the clock edge that the RDEN is activated. In other words, data is available 1 clock cycle later as compared to scenario #1, which is the 2nd clock edge after RDEN is activated.

  3. With output register and using RDEN to control the output register, the data will be available the same time as in scenario #2 provided the RDEN is still active during the 2nd clock edge. This is because the output register is controlled by the RDEN and it needs RDEN to be active to clock in the data.
The clock referred in this explanation is the Rd_Clock of the FIFO_DC.