Description:
An iteration limit error may appear when simulating using the PCS IP core.
Solution:
There are several possible causes for the Iteration Limit Errors.
- The polarities of the PCS resets are incorrect. When the SERDES Quad reset is removed, an iteration limit error occurs.
- Incorrect simulation time parameters are used, such as a timescale that is too large (>fs).
- There is a clock used in a part of the design that has the same name as a PCS clock that is used. This can cause conflicts in the simulation.
- For ECP2M SERDES, the power-up reset sequence is not followed. You must power up with the reset de-asserted, then assert it, then de-assert it.
- X's are being sent to PLL inputs or other element inputs.
- Other IP models or codes are used in the simulation with the same instance names. These can cause conflicts in the lattice IP models.