N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation

Aggregate multiple Image Sensors into a single Output with Minimal Latency

Managing multiple CSI-2 sensors: Cameras have become ubiquitous and numerous in many of today’s applications. System designers are challenged with moving data from multiple CSI-2 sensors into an Applications Processor (AP), where it can be further processed. To help overcome the limits of AP input resources, data from multiple cameras can be aggregated to a single stream.

Connecting with CrossLink: The Lattice CrossLink FPGA family combines the flexibility of an FPGA with high-performance hardened D-PHY ports, ideally suited to solve many video bridging, aggregation and ISP design challenges.

Complete Reference Design: This reference design concatenates up to 5 channels horizontally line by line. The N Input to 1 Output MIPI CSI-2 Side-by-Side Aggregation Reference Design includes a thoroughly documented design example powered by Lattice CSI-2/DSI D-PHY Receiver and CSI-2/DSI D-PHY IP cores.

Features

  • Aggregate up to 5 MIPI CSI-2 input channels horizontally, each with up to four lanes (up to 15 total Rx clock and data lanes to soft IP)
  • Uses a combination of soft or hard MIPI-compliant IP
  • Maximum 1.2 Gpbs Rx per lane
  • One, Two or Four Tx lanes
  • Maximum 1.5 Gbps Tx per lane (6 Gbps maximum bandwidth)

Jump to

Block Diagram

Documentation

Technical Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
CSI-2 Side-by-side Aggregation Reference Design for CrossLink – Documentation
FPGA-RD-02192 1.0 5/1/2020 PDF 1.8 MB
CSI-2 Side-by-side Aggregation Reference Design for CrossLink – Source Code
1.0 5/1/2020 ZIP 18.9 MB


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