CSI-2/DSI D-PHY Receiver IP Core

Convert MIPI CSI-2/DSI Data Streams to Parallel Data

The Mobile Industry Processor Interface (MIPI®) D-PHY was developed primarily to support camera and display interconnections in mobile devices, and it has become the industry’s primary high-speed PHY solution for these applications in smartphones. It is typically used in conjunction with MIPI Camera Serial Interface-2 (CSI-2) and MIPI Display Serial Interface (DSI) protocol specifications. MIPI D-PHY meets the demanding requirements of low power, low noise generation, and high noise immunity that mobile phone designs demand.

MIPI D-PHY is a practical PHY for typical camera and display applications. It is designed to replace traditional parallel bus based on LVCMOS or LVDS. Lattice’s submodule may be used for applications requiring a D-PHY receiver in the FPGA logic.

Features

  • Compliant with MIPI DSI v1.1, MIPI CSI-2 v1.1 and MIPI D-PHY v1.1 specifications
  • Supports MIPI DSI and MIPI CSI-2 interfacing up to 10 Gb/s
  • Supports 1, 2 or 4 MIPI D-PHY data lanes
  • Supports non-burst mode with sync events for transmission of DSI packets only
  • Supports LP (low power) mode during vertical and horizontal blanking

Block Diagram

CSI-2/DSI D-PHY Receiver

Resource Utilization

IP Configuration for Nexus Family
Lane
(Gear)
RX Interface Type IP Type Bit Rate
(Lane)
Parser AXI Bus LMMI Bus Registers LUT2 EBR High-Speed I/O esources
4(8) CSI-2 Hard D-PHY4 1000 Mbps EN EN DIS 629 699 2 1 x Hard D-PHY
4(8) CSI-2 Soft D-PHY 1000 Mbps EN EN DIS 706 1212 2 4 x IDDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4(16)3 CSI-2 Hard D-PHY4 2500 Mbps EN EN DIS 852 991 4 1 x Hard D-PHY
4(8)3 CSI-2 Soft D-PHY4 1500 Mbps EN EN DIS 706 1270 2 4 x IDDRX4,
1 x ECLKDIV,
1 x ECLKSYNC
4(16) DSI Hard D-PHY4 2000 Mbps EN EN EN 1006 1520 4 1 x Hard D-PHY
4(16) DSI Hard D-PHY5 2000 Mbps EN EN EN 1006 1520 4 1 x Hard D-PHY
4(8) DSI Hard D-PHY4 1200 Mbps EN EN DIS 682 843 2 1 x Hard D-PHY
2(8) DSI Hard D-PHY4 800 Mbps EN DIS DIS 448 566 2 1 x Hard D-PHY
4(16)3 CSI-2 Hard D-PHY4 2500 Mbps EN EN EN 870 1041 4 1 x Hard D-PHY
4(8)3 CSI-2 Hard D-PHY4 1500 Mbps EN EN EN 585 747 2 1 x Hard D-PHY
2(8) CSI-2 Hard D-PHY4 800 Mbps EN DIS DIS 447 554 2 1 x Hard D-PHY

1. All other settings are default.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.
3. Data Settle settings were changed in these configurations to match their target Bit Rate per Lane.
4. Hard D-PHY – CIL Bypassed
5. Hard D-PHY – CIL Enabled
For more information regarding a specific configuration, the user can generate the IP, run synthesis and MAP, and check the MAP reports for resource utilization.

To view the complete Resource Utilization of the CSI-2/DSI D-PHY Receiver IP Core, click here to view the table.

Ordering Information

The CSI-2 DSI D-PHY Receiver core is available for FREE for use in Diamond design software.

For Radiant design software, the CSI-2 DSI D-PHY Receiver core must be purchased:

  Part Number
Device Family Multi-site Perpetual Single Seat Annual
Avant-G DPHY-RX-AVG-UT DPHY-RX-AVG-US
Avant-X DPHY-RX-AVX-UT DPHY-RX-AVX-US
Avant-E DPHY-RX-AVE-UT DPHY-RX-AVE-US
MachXO5-NX DPHY-RX-XO5-UT DPHY-RX-XO5-US
CertusPro-NX DPHY-RX-CPNX-UT DPHY-RX-CPNX-US
CrossLink-NX DPHY-RX-CNX-UT DPHY-RX-CNX-US
Certus-NX DPHY-RX-CTNX-UT DPHY-RX-CTNX-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the CSI-2/D-PHY Receiver IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CSI2/DSI D-PHY Receiver IP Core User Guide for Diamond Design Software
FPGA-IPUG-02025 1.5 11/24/2021 PDF 1.3 MB
CSI-2/DSI D-PHY Rx IP Core - Lattice Radiant Software
FPGA-IPUG-02081 2.1 2/2/2024 PDF 1.5 MB

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