1 to N MIPI CSI-2/DSI Duplicator

Duplicate one MIPI RX channel to one or two MIPI TX channels

Targeting Video Applications: Many new applications such as virtual reality, augmented reality, and digital cameras require expansion of the number of camera or display interfaces on application processors (AP).

Connecting with CrossLink and CrossLink-NX: The Lattice CrossLink and CrossLink-NX FPGA families combines the flexibility of an FPGA with high-performance hardened D-PHY ports, ideally suited to solve many video bridging, aggregation and ISP design challenges.

Complete Reference Design: The 1 to N MIPI CSI-2/DSI Duplicator reference design for CrossLink and CrossLink-NX devices provides a duplicate of the input channel for one or two channel outputs.


  • One RX channel is duplicated to one or two TX channels (RX / TX channel can have one, two, or four lanes)
  • For RX, Hard IP enables 1.5 Gbps per lane and saves FPGA resources. Soft IP performance is 1.2 Gbps per lane.
  • Hard IP is used on TX channel(s), enabling 1.5 Gbps per lane performance
  • Non-continuous clock mode on RX channels is possible provided the continuous clock can be obtained internally or fed directly from the pin.
  • Maximum 1.5 Gbps Tx per lane (10 Gbps maximum bandwidth)

Jump to

Block Diagram


Technical Resources
1 to N MIPI CSI-2/DSI Duplicator with CertusPro-NX - Source Code
FPGA-RD-02240 1.0 9/17/2021 ZIP 20.2 MB
CSI-2 / DSI Duplicator Reference Design for CrossLink – Documentation
FPGA-RD-02194 1.0 5/1/2020 PDF 1.6 MB
CSI-2 / DSI Duplicator Reference Design for CrossLink – Source Code
1.0 5/1/2020 ZIP 13.1 MB
1 to N MIPI CSI-2/DSI Duplicator with CertusPro-NX - Documentation
FPGA-RD-02240 1.0 9/17/2021 PDF 1.8 MB

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