CNN Co-Processor Accelerator IP

SoC based AI Acceleration using Low Power Lattice FPGAs

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A powerful acceleration engine – CNN co-processor engine IP leverages the parallel compute, DSP block, and distributed memory features of low power Lattice FPGAs.

Easy to implement – Lattice Propel provides an environment to develop an SoC featuring a RISC-V processor, CNN co-processing engine, and other peripherals on Lattice FPGAs so developers can build SoC that capitalize on FPGA’s parallel processing capabilities.

TF Lite Support – Designs built on TF Lite can be ported to Lattice FPGAs without requiring previous experience with FPGA hardware design.

Features

  • Selectable AXI4 or FIFO interface
  • Support for convolution layer, max pooling layer, global average pooling layer, batch normalization layer, and a fully-connected layer
  • Configurable bit width of activation (16- and 8-bit)
  • Configurable number of memory blocks lets developers optimize designs for resource or performance
  • Optimized for 3 × 3 2D convolution calculations and dynamic support for various 1D convolutions (from 1 to 9 taps)

Block Diagram

Ordering Information

Family Part Number
Single Design Multi-Site
CertusPro-NX CNN-COPROC-CPNX-U CNN-COPROC-CPNX-UT
Certus-NX CNN-COPROC-CTNX-U CNN-COPROC-CTNX-UT
CrossLink-NX CNNP-COPROC-CNX-U CNNP-COPROC-CNX-UT

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
CNN Co-Processor Accelerator IP User Guide
FPGA-IPUG-02170 1.0 11/10/2021 PDF 1.2 MB

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