SWAP-C FPGAs for Aerospace and Defense

Meet mission requirements with low power and high reliability Lattice FPGAs

Our system is going under maintenance starting April 18, 2025 at 6:00 PM Pacific and ending April 20, 2025 at 4:00 PM Pacific. During this window, the website may not be reachable. For immediate assistance, please contact techsupport@latticesemi.com.

Related Products

Related Applications


Newsletter Subscription

Accelerate design cycles, reduce system costs and future proof designs with programmable solutions for a multitude of application from airborne platforms, communication systems, ISR and space missions. With over 40 years of heritage in delivering low power, programmable solutions, Lattice Semiconductor has a rich history of delivering SWAP-C optimized FPGAs for connectivity, signal processing, sensor fusion and machine learning solutions developed from ground-up to address the industry needs.

  • Industry leading low power FPGAs to meet thermal constraints and rugged application requirements
  • Innovative silicon and software solutions to meet domain specific safety, security and reliability requirements
  • World’s largest volume FPGA vendor with a robust supply chain built for assurance and longevity

Key Lattice FPGA Features & Benefits

  • Low power FPGAs that scale up to 637k System Logic Cells and up to 28 instances of 25Gbps Serdes optimized for edge connectivity and signal processing
  • Industry leading advanced security features including AES256-GCM, ECDSA 256-521 & RSA 2048-4096 with post quantum resilience, anti-tamper and hardened PUF to secure bitstream and protect user data during run-time
  • Low soft error rate, latch-up immunity (80 (MeVcm2)/mg @ T=125°C) with industry leading fast, hardened scrubber (SEDC) and fast secure boot independent of configuration bit technology
  • Design tools offer latest advancements in scripting, design partioning, timing analysis, high speed interface debug and third party tools integration for synthesis including TMR, simulation and verification

Defense

Jump to

Example Applications

Sensor Bridge Reference Design Block DiagramExpand Image

Sensor Bridge Reference Design

  • Scalable, Low latency, open source sensor to compute platform
  • Diverse sensor connections from MIPI to RFs
  • RTL-based data plane and control plane packetizer
  • Easy programming and system control
Robot Vision and Control Block DiagramExpand Image

Robot Vision and Control

  • Multi-channel Camera / sensor bridging and aggregation
  • Multi-channel Camera / sensor pre-processing and synchronization
  • Real time sync, sense & control, multi-axis
  • Internal Soft CPU and/or External CPU
Use Case Block Diagram: Packet Processing and Board ControlExpand Image

Packet Processing and Board Control

  • Bridge CPU via PCIe to multiple control plane peripherals (I2C, UART, GPIO), board management functions, and up to 25GE control plane traffic
  • Security functions (e.g., encryption, authentication) implemented in FPGA helps secure control plane traffic
  • 25G SerDes supporting PCIe Gen 4 x4 (in hard IP) and 25 Gigabit Ethernet
  • Fast FPGA configuration supports board management needs and PCIe boot-time requirements
Control Plane Security and Hardware ManagementExpand Image

Control Plane Security and Hardware Management

  • Bridge CPU via PCIe to multiple control plane peripherals (I2C, UART, GPIO), board management functions, and 10GE control plane traffic
  • Security functions (e.g., encryption, authentication) implemented in FPGA helps secure control plane traffic
  • 10G SERDES supporting PCIe Gen 3 x4 (in hard IP) and 10 Gigabit Ethernet (with 10GBASE-R PCS in hard IP)
  • High system reliability and up-time due to 100x lower Soft Error Rate (SER) from FD-SOI technology
  • Fast FPGA configuration supports board management needs and PCIe boot-time requirements
Lattice ORAN IEEE 1588 PTP Secure Sync Block DiagramExpand Image

Secure Synchronization with Compliant 1588 PTP

High precision 1588 PTP time, frequency and phase synchronization, Supports secure authentication, message integrity and replay attack protection, Instant-on performance with better than Class C timing accuracy ,Complete customizable hardware and software solution to enable distributed architecture.

Smart Munitions Block DiagramExpand Image

Guidance Systems

  • Programmable system integration with 5Gbps transceivers, embedded memory, DSP and MCU
  • Sensor fusion, any-to-any connectivity and embedded vision
Chain of Trust Implementation ExampleExpand Image

Chain of Trust Implementation

  • Hardware Root-of-Trust is the first link in chain that protects mission critical compute and communication platforms
  • Hardened device configuration engine cryptographically authenticates MachXO3D’s configuration image at power-on
  • Embedded security block provides cryptographic functions to authenticate other platform firmware at power-on
Mixed Reality Head Mount Display Block DiagramExpand Image

Mixed Reality Head-Mount Display

  • Small form factor packaging to meet stringent signal processing requirements
  • Flexible interfaces to sensors, analog and RF front-ends

FPGAs Best Suited for Defense

  • Avant-X
    Avant-X FPGAs delivers the industry’s lowest power mid-range FPGA in small packages, enabling a cost effective solution for applications that require sensor processing, high-speed connectivity and proven reliability. With 28 Multi-protocol transceivers, class leading anti-tamper and latch-up immunity in harsh environments, Avant-X is well suited for advanced, integrated Aerospace & Defense solutions.
  • CertusPro-NX
    CertusPro-NX is optimized for bandwidth to compute density to help maximize system performance in small form factor. Leveraging the low power architecture and up to 8 ports of 10Gbps serdes coupled with a flexible wide range and high speed I/O for LPDDR4 simplify system design while keeping the FPGA power under 1W. Based on Nexus platform, the FPGA has been extensively tested for reliable operation in harsh environements.
  • Certus-NX
    Certus-NX is Built on Lattice Nexus platform with Up to 4x lower power vs. similar FPGAs and Up to 100x higher reliability based on 28 nm FD-SOI technology solves the most challenging problems in leading edge defense platforms.
  • CrossLink-NX
    The Crosslink-NX with low soft error rate and lowest power in its class enables efficient processing, bridging and management capabilities to solve challenging problems in Software Defined Radios, Guidance Systems and Unmanned Aerial Vehicle (UAV).
  • MachXO3D
    The MachXO3D is the root of trust enabler with all required features onboard on a monolithic silicon with small footprint and low power that could be deployed in systems of all sizes, offering the most compact solution for untrusted supply chain.

Leaded Package Overview

Lattice offers leaded packaging services to eliminate the risk for tin-whisker and to improve reliability in presence of high shock and vibration applications.

Lattice Packages Wirebond Flip Chip
Wafer Pad or Bump Lead free Lead free
Substrate bump or pad finish Lead free Lead free
Caps No Caps No Caps
Substrate Solder Balls Leaded Leaded
Package Reflow Leaded Leaded

Known Good Die Product Overview

Lattice offers a wide variety of known good die products, tested to full data sheet specification within the specified temperature range with full traceability for each die shipped.

Family Logic Density Test Method Programmability Temperature Range
LatticeECP3 150K Known Good Die Volatile -40 C to 125 C
LatticeXP2 40K Good Die Non-volatile -40 C to 125 C
ECP5 85K Known Good Die Volatile -40 C to 125 C
MachXO3 10K Known Good Die Non-volatile -40 C to 105 C

Reference Designs

GHRD/GSRD Reference Design

Reference Design

GHRD/GSRD Reference Design

The Golden Hardware and Software Reference Design comprises of components for developing various kind of applications using CertusPro-NX Versa Board.
CertusPro-NX, Avant-E 
GHRD, GSRD, RISC-V, AXI4, MPMC, Lattice Automate, Defense 
Lattice Sentry 4.0 SCM and HPM CPLD Reference Design

Reference Design

Lattice Sentry 4.0 SCM and HPM CPLD Reference Design

​​This is a CPLD design template for the Secure Control Module (SCM) and Host Platform Module (HPM) for the Sentry 4.0 Server solution platform.​
MachXO3D, MachXO3 
SCM, HPM, CPLD, Lattice Sentry, Security, Defense, LTPI, MPESTI, SGPIO, eSPI 
Lattice Sentry 4.0 SCM and HPM CPLD Reference Design
Scene Segmentation Reference Design

Reference Design

Scene Segmentation Reference Design

Efficient and low power approach for implementing scene segmentation using Lattice CrossLink-NX FPGA
CrossLink-NX 
Lattice sensAI, Machine Learning/AI, SPI, Object Counting, Object Segmentation, Image Processing, Camera, Defense 
Scene Segmentation Reference Design
Redundant Power Supply Management

Reference Design

Redundant Power Supply Management

Uses a Lattice Power Manager II device to achieve Redundant Power Supply Management using the power supply OR’ing technique
Power Manager II 
Mixed-Signal, Power Management, Guidance Systems, Defense, SDR 
Redundant Power Supply Management
Lattice Sentry Root of Trust Reference Design for MachXO3D

Reference Design

Lattice Sentry Root of Trust Reference Design for MachXO3D

This design utilizes Lattice Sentry IP to help you develop and test a complete NIST 800-193-compliant PFR solution. You can modify to suit your specific needs.
MachXO3D 
NIST, RISC-V, Lattice Propel, Lattice Sentry, Security, Defense 
Lattice Sentry Root of Trust Reference Design for MachXO3D
Show More

IP Cores

Image Signal Processing IP Cores Suite

IP Core

Image Signal Processing IP Cores Suite

The Lattice mVision ISP IP Core implements ISP pipelines for image quality enhancements in embedded designs based on Lattice FPGA devices.
CrossLink-NX, Certus-NX, CertusPro-NX, Avant-E 
AXI, AXI-Stream, AXI-Lite Interface, AWB, Camera, CCM, CFA Interpolation, Debayer, Image Processing, Image Signal Processing, Lattice mVision, RGB, Defense 
Image Signal Processing IP Cores Suite
PCI Express for Nexus FPGAs

IP Core

PCI Express for Nexus FPGAs

The Lattice PCIe IP Core provides a flexible, high-performance, easy-to-use Transaction Layer Interface to the PCI Express Bus.
CrossLink-NX, Certus-NX, CertusPro-NX, MachXO5-NX 
APB, AHB, AHB-Lite, RTL, PCI, PCIe, Bus Controllers, Defense, Automotive, PCIe Bundle, SDR 
PCI Express for Nexus FPGAs
RISC-V MC CPU IP Core

IP Core

RISC-V MC CPU IP Core

The Lattice RISC-V MC CPU soft IP contains a 32-bit RISC-V processor core and optional submodules – Timer and Programmable Interrupt Controller (PIC).
MachXO3D, Certus-NX, CrossLink-NX, Avant-E, MachXO5-NX, CertusPro-NX, MachXO3, MachXO2, Avant-G, Avant-X 
AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 
RISC-V MC CPU IP Core
RISC-V SM CPU IP Core

IP Core

RISC-V SM CPU IP Core

Lattice RISC-V SM CPU IP core supports the RV32I instruction set, external interrupt, and debug feature, which is JTAG – IEEE 1149.1 compliant.
Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, MachXO3D, MachXO3, MachXO2, Avant-G, Avant-X 
AHB-Lite, Soft Processor, RISC-V, Lattice Propel, TOR Switch, Defense, Automotive, SDR 
RISC-V SM CPU IP Core
RISC-V RX CPU IP Core

IP Core

RISC-V RX CPU IP Core

Lattice RISC-V RX IP processes data and instructions while monitoring the external interrupts, using 32-bit RISC-V processor core and several submodules.
Avant-E, MachXO5-NX, Certus-NX, CertusPro-NX, CrossLink-NX, Avant-G, Avant-X 
AHB-Lite, Soft Processor, RISC-V, RTOS, Lattice Propel, Defense, Automotive 
RISC-V RX CPU IP Core
Show More

Development Kits & Boards

Avant-E Evaluation Board

Board

Avant-E Evaluation Board

The Avant-E Evaluation Board has the ability to expand the usability of the Avant-E FPGA with FMC HPC, PMOD, and Raspberry PI connectors.
Avant-E 
Lattice Avant, SPI Flash, LPDDR4, SERDES, GPIO, PMOD, FMC, Industrial Networking, SDR, Defense, Lattice Automate, Lattice sensAI 
Avant-E Evaluation Board
Avant-X Versa Board

Board

Avant-X Versa Board

Avant-X Versa Board support devices that offers a modernized feature set for accelerated system design and fastest soft error detect (SED).
Avant-X 
Lattice Avant, SPI Flash, DDR5, LPDDR4, SERDES, GPIO, PMOD, FMC, Industrial Networking, SDR, Defense 
Avant-X Versa Board
Space Development Board by Adiuvo

Board

Space Development Board by Adiuvo

Developed by a team of experienced engineers for space and with prototyping space applications in mind, the board provides access to the commercial equivalent of the space grade Certus™-NX-RT, making it ideal for prototyping and test campaigns to increase the Technology Readiness Level.
Certus-NX 
Community Sourced, Raspberry Pi, SpaceWire, Defense 
Space Development Board by Adiuvo
LimeSDR Mini Development Board by Lime Microsystems

Board

LimeSDR Mini Development Board by Lime Microsystems

LimeSDR Mini Dev Board is a low cost, open source and apps-enabled SDR platform that can be used to support any type of wireless communication standard.
ECP5 / ECP5-5G 
Community Sourced, RF Transceiver, FTDI, GPIO, JTAG, Defense, SDR 
LimeSDR Mini Development Board by Lime Microsystems
Lattice Sentry 4.0 Demo Board for MachXO5-NX

Board

Lattice Sentry 4.0 Demo Board for MachXO5-NX

A complete platform to help you develop and test a NIST 800-193-compliant PFR solution and help in SoC project in Lattice Radiant and Propel 2024.1 Tools.
MachXO5-NX 
Defense, Security, Lattice Sentry, PFR, RoT 
Lattice Sentry 4.0 Demo Board for MachXO5-NX
Show More

Demos

GHRD/GSRD Demonstration

Demo

GHRD/GSRD Demonstration

The Golden Hardware and Software Reference Design comprises of components for developing various kind of applications using CertusPro-NX Versa Board.
CertusPro-NX, Avant-E 
GHRD, GSRD, RISC-V, AXI4, MPMC, Lattice Automate, Defense 
GHRD/GSRD Demonstration
MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

Demo

MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration

This demo illustrates L-ASC10 integration in a MachXO5-NX design and demonstrates RISC-V SOC interfacing with power sequencing and fault response.
MachXO5-NX 
L-ASC10, RISC-V, Defense, SDR 
MachXO5-NX and L-ASC10 Platform Power Management Using RISC-V Demonstration
Lattice Image Signal Processing Demo

Demo

Lattice Image Signal Processing Demo

Provides a complete ISP example design on the Lattice ECP5 FPGA for the Embedded Vision Development Kit, ideal for Industrial, Medical, and Automotive applications.
ECP5 / ECP5-5G, CertusPro-NX 
Image Signal Processing, Lattice mVision, Space, Defense 
Lattice Image Signal Processing Demo
Power Sequencing with Fault Logging Demo

Demo

Power Sequencing with Fault Logging Demo

Uses L-ASC10 to monitor, sequence four separate Power Planes from a central control point. Logs faults with timestamps. Expandable.
Platform Manager 2 & L-ASC10, MachXO3 
Mixed-Signal, Power Management, TOR Switch, Guidance Systems, 5G, Defense, SDR 
Power Sequencing with Fault Logging Demo
PCIe Basic Demo for Lattice Nexus-based FPGAs

Demo

PCIe Basic Demo for Lattice Nexus-based FPGAs

The PCIe Basic Demo allows you to control three 7 segment LEDs and manipulate the onboard memory of the FPGA through the PCIe slot.
CrossLink-NX, Certus-NX, CertusPro-NX 
SPI, Camera, CSI Camera, Ethernet, PCIe, PMOD, RJ-45, X/S/RGMII, UAVs, Automotive, Bus Controllers, Defense, LED, Nexus PCIe 
PCIe Basic Demo for Lattice Nexus-based FPGAs
Show More

Quality Programs

Lattice is committed to Industry Leadership in the supply of high quality programmable logic components and software design tools.

Commitment to Defense

Lattice is committed to providing the Defense market with industry’s most complete portfolio optimized for SWAP-C, longest product life cycle and dedicated local engineering support.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.6 8/1/2024 PDF 368 KB
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.1 3/15/2021 PDF 855.2 KB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.1 7/18/2024 PDF 614.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Single Event Upset (SEU) Report for Nexus Platform
FPGA-TN-02174 1.6 8/1/2024 PDF 368 KB
Implementing JOTP-051-Compliant Safety Features in Lattice FPGAs
FPGA-TN-02150 1.1 3/15/2021 PDF 855.2 KB
Soft Error Detection (SED)/Correction (SEC) User Guide for Nexus Platform
FPGA-TN-02076 2.1 7/18/2024 PDF 614.6 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Defense Solutions Brief
I0271 Rev 1 8/4/2020 PDF 1.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
A Guide to the Benefits of the Lattice Nexus FPGA Platform for Mission-Critical Applications
WP0028 1.0 1/22/2021 PDF 449.4 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

Support

Technical Support

Need Help? We're Here to Assist You

Licensing

Find The Software & IP Licenses You Need

Quality & Reliability

Reference Material to Help Answer Your Questions

Services

Outside Services to Help Get The Job Done

Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.

ABOUT LATTICE

SALES

SUPPORT

FOLLOW