The Lattice Internal Flash Controller for MachXO5-NX IP Core has a system bus interface to access the registers. The input bus can be configured through IP attributes, which can be either AHB-Lite or APB interface. This IP also has four sub-blocks: Register Block, Data Buffer, Controller, and Flash Memory.
The Internal Flash Controller IP Core is available for free to use in Lattice Radiant design software.
Quick Reference | Information Resources |
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| Internal Flash Controller Driver API Reference | FPGA-TN-02421 | 1.0 | 12/11/2025 | 493 KB | |||
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| Internal Flash Controller IP Core for MachXO5-NX - User Guide | FPGA-IPUG-02174 | 1.8 | 2/18/2026 | 1.5 MB | |||
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| Internal Flash Controller IP Core for MachXO5-NX - Release Notes | FPGA-RN-02085 | 1.3 | 6/26/2026 | 329.8 KB | |||
