Memory Controller IP Core

Supports DDR3 and LPDDR4, compliant to JESD79-3, JESD209-4 SDRAM Standard

The Lattice Semiconductor Memory Controller Interface module provides a solution to interface to DDR3 or LPDDR4 DDR memory standards. Lattice provides a turnkey solution with controller, DDR PHY, the associated clocking scheme, and training related logic.

The Lattice Memory Controller IP supports JEDEC compliant JESD79-3C DDR3 and JESD209-4C LPDDR4 standards.

The Memory Controller IP reduces the effort required to integrate the DDR3 memory controller with the user application design and minimizes the need to directly deal with the DDR3/LPDDR4 memory interface by providing AHB-L standard interface.


  • Memory Controller supports DDR3 and LPDDR4, compliant to JESD79-3, JESD209-4 SDRAM standard
  • Speeds of up to 533 MHz command or data speeds of 1066 MTps
  • Configurable address widths to support various densities
  • DDR3 widths ranging from x8 to x64
  • Support for SEC DED ECC

Jump to

Block Diagram

Ordering Information

Family License Type Ordering Part Number
CertusPro-NX Single-Design License LPDDR4-MC-CPNX-U
Multi-Site License LPDDR4-MC-CPNX-UT


Quick Reference
Memory Controller IP Core - Lattice Radiant Software
FPGA-IPUG-02127 1.3 2/23/2022 PDF 1.7 MB
Memory Modules - Lattice Radiant Software
FPGA-IPUG-02033 2.5 6/23/2021 PDF 2.4 MB

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