Memory Controller IP Core

Supports LPDDR4, compliant to JESD209-4 SDRAM Standard

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The Lattice Semiconductor Memory Controller Interface module provides a solution to interface to LPDDR4 DDR memory standards. Lattice provides a turnkey solution with controller, DDR PHY, the associated clocking scheme and training related logic. The design is implemented in System Verilog HDL. The IP Core can be targeted to the LatticeAvant™ LAV-AT FPGA devices. The IP Core is implemented using the Lattice Radiant™ software integrated with the Synplify Pro® synthesis tool.

The Lattice Memory Controller IP supports JEDEC compliant JESD209-4C LPDDR4 standard. The Memory Controller IP reduces the effort required to integrate the LPDDR4 memory controller with the user application design and minimizes the need to directly deal with the LPDDR4 memory interface by providing AXI4 Data Interface.

Features

  • Memory Controller supports LPDDR4, compliant to JESD209-4 SDRAM standard
  • Speeds of up to 533 MHz command or data speeds of 1066 MTps
  • Configurable address widths to support various memory densities
  • DDR widths of x16, x32, and x64
  • Burst length BL16/32 OTF

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Block Diagram

Memory Controller IP Core Block DiagramExpand Image

Resource Utilization

Avant Family
LAV-AT-500E-2LFG1156C
Configuration clk_i Fmax (MHz) sclk_o Fmax (MHz)1 Registers LUTs EBR DSP
DDR Bus Width =16,
Others=default		 262.055 235.905 5500 8328 13 0
Default 236.574 209.38 6488 8841 17 0
DDR Bus Width =64,
Others=default		 218.579 202.143 8342 9501 25 0
DDR Bus Width =64,
Enable Power Down is Checked,
Enable DBI is Checked,
Others=default		 239.923 221.484 8493 11398 25 0

Note: 1. The sclk_o Fmax is generated using the eval_top.v

Nexus Family
LFCPNX-100-9FFG672I (IP Core v1.3.01)
Configuration sclk_o Fmax (MHz)1 Registers LUTs EBR IDDR/ODDR/TDDR
Interface Type = Native
Default		 139.567 5709 9235 18 121 (32+49+40)
Interface Type = Native
Enable DBI=Checked,
Enable Power Down=Checked,
Others = Default		 140.984 5802 9873 18 125 (36+49+50)
Interface Type = Native
Enable Internal RISC-V CPU=Unchecked,
Others = Default		 143.554 5006 7853 8 121 (32+49+40)
Interface Type = Native
DDR Bus Width=16,
Others = Default		 136.519 4332 7062 14 65 (16+29+20)
Interface Type = Native
DDR Bus Width=64,
Others = Default		 141.243 8071 12790 26 233(64+89+80)
Interface Type = AHBL
Others = Default 		143.761 6935 10396 18 121 (32+49+40)
Interface Type = AHBL,
Enable DBI = Checked,
Enable Power Down = Checked,
Others = Default		 141.761 6935 10969 18 125 (36+49+50)
Interface Type = AHBL,
Enable Internal RISC-V CPU = Unchecked,
Others = Default 		140.905 6234 8987 8 121 (32+49+40)
Interface Type = AHBL,
DDR Bus Width = 16,
Others = Default		 134.246 5296 8061 14 65 (16+29+20)
Interface Type = AHBL,
DDR Bus Width = 64,
Others = Default		 124.719 10228 15526 26 233 (64+89+80)

Note: 1. The sclk_o Fmax is generated using the eval_top.v. These values may increase when the IP Core is used with the user logic.

LFCPNX-100-9FFG672C (IP Core v2.0.01)
Configuration clk_i Fmax (MHz) sclk_o Fmax (MHz)1 Registers LUTs EBR IDDR/ODDR/TDDR
DDR Bus Width =16,
Others=default		 157.953 151.7914 7417 11096 16 16/30/20
Default 139.548 157.456 8624 12359 33 32/50/40
DDR Bus Width =64,
Others=default		 135.52 150.308 10859 14748 50 64/90/80
DDR Bus Width =64,
Enable Power Down is Checked,
Enable DBI is Checked,
Others=default		 127.992 140.528 10987 16182 50 72/90/80

Note: 1. The sclk_o Fmax is generated using the eval_top.v. These values may increase when the IP Core is used with the user logic.

Ordering Information

Device Family Part Numbers
Single Design Multi-Site Subscription
Avant-E LPDDR4-PHY-AVE-U LPDDR4-PHY-AVE-UT LPDDR4-PHY-AVE-US
CertusPro-NX LPDDR4-MC-CPNX-U LPDDR4-MC-CPNX-UT LPDDR4-MC-CPNX-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the LPDDR4 IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Avant Memory Controller IP Core - User Guide
FPGA-IPUG-02208 1.1 10/1/2023 PDF 920.6 KB
LPDDR4 Memory Controller for Nexus Devices
FPGA-IPUG-02127 1.5 9/18/2023 PDF 2.7 MB
Memory Modules - Lattice Radiant Software
FPGA-IPUG-02033 2.5 6/23/2021 PDF 2.4 MB

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