The Lattice Semiconductor Memory Controller Interface module provides a solution to interface to LPDDR4 DDR memory standards. Lattice provides a turnkey solution with controller, DDR PHY, the associated clocking scheme and training related logic. The design is implemented in System Verilog HDL. The IP Core can be targeted to the LatticeAvant™ LAV-AT FPGA devices. The IP Core is implemented using the Lattice Radiant™ software integrated with the Synplify Pro® synthesis tool.
The Lattice Memory Controller IP supports JEDEC compliant JESD209-4C LPDDR4 standard. The Memory Controller IP reduces the effort required to integrate the LPDDR4 memory controller with the user application design and minimizes the need to directly deal with the LPDDR4 memory interface by providing AXI4 Data Interface.