Memory Controller IP Core

Supports LPDDR4, compliant to JESD209-4 SDRAM Standard

Our system is going under maintenance on August 13th between 2:00 pm to 10:00 pm Pacific. During this window, the website may not be reachable. For immediate assistance, please contact techsupport@latticesemi.com.

Related Products

Related Applications

The Lattice Semiconductor Memory Controller Interface module provides a solution to interface to LPDDR4 DDR memory standards. Lattice provides a turnkey solution with controller, DDR PHY, the associated clocking scheme and training related logic.

The Lattice Memory Controller IP supports JEDEC compliant JESD209-4C LPDDR4 standard.

The Memory Controller IP reduces the effort required to integrate the LPDDR4 memory controller with the user application design and minimizes the need to directly deal with the LPDDR4 memory interface by providing AHB-L standard interface or Native Interface.

Features

  • Memory Controller supports LPDDR4, compliant to JESD209-4 SDRAM standard
  • Speeds of up to 533 MHz command or data speeds of 1066 MTps
  • Configurable address widths to support various memory densities
  • DDR widths of x16, x32, and x64
  • Burst length BL16/32 OTF

Jump to

Block Diagram

Ordering Information

Family License Type Ordering Part Number
CertusPro-NX Single-Design License LPDDR4-MC-CPNX-U
Multi-Site License LPDDR4-MC-CPNX-UT

Documentation

Quick Reference
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Memory Controller IP Core - Lattice Radiant Software
FPGA-IPUG-02127 1.3 2/23/2022 PDF 1.7 MB
Memory Modules - Lattice Radiant Software
FPGA-IPUG-02033 2.5 6/23/2021 PDF 2.4 MB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

Like most websites, we use cookies and similar technologies to enhance your user experience. We also allow third parties to place cookies on our website. By continuing to use this website you consent to the use of cookies as described in our Cookie Policy.