Memory Controller IP Core

A Turnkey Solution Supporting DDR4 and LPDDR4 SDRAM, Compliant to JEDEC Standard

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The Lattice Semiconductor DDR Memory Controller IP provides a turnkey solution consisting of a controller, DDRPHY, and associated clocking and training logic to interface with DDR4 and LPDDR4 SDRAM.

This IP supports all the Lattice Nexus 2, Avant, and Nexus device families for the following modes:

DDR4 and LPDDR4 mode:
Lattice Avant (Avant-E, Avant-G, Avant-X) and Lattice Nexus 2 (Certus-N2)

LPDDR4 mode only:
Lattice Nexus (CertusPro-NX, MachXO5T-NX)

Resource Utilization details are available in the DDR Memory Controller IP Core User Guide and LPDDR4 Memory Controller IP Core for Nexus Devices User Guide.

Features

DDR4 mode (Avant and Nexus 2)

  • DDR4 SDRAM protocol, compliant to DDR4 JEDEC Standard.
  • DDR4 SDRAM speeds up to 1200 MHz/2400 Mbps for speed grade 3 devices, up to 1066 MHz/2133 Mbps for speed grade 2, and up to 933 MHz / 1066 Mbps for speed grade 1.
    (Dual-rank configurations are only supported on speed grades 2 and 3)
  • Component support for interface data widths of x16, x32, and x64.
  • Up to 16 Gb density support.

LPDDR4 mode (Avant and Nexus 2)

  • LPDDR4 SDRAM protocol, compliant to LPDDR4 JEDEC Standard.
  • LPDDR4 SDRAM speeds up to 1200 MHz/2400 Mbps for speed grade 3 devices and up to 1066 MHz/2133 Mbps for speed grade2, and up to 933 MHz / 1066 Mbps for speed grade 1.
    (Dual-rank configurations are only supported on speed grades 2 and 3)
  • Component support for interface data widths of x16, x32, and x64.
  • Up to 16 Gb density support per channel

LPDDR4 mode (Nexus)

  • LPDDR4 SDRAM protocol, compliant to LPDDR4 JEDEC Standard.
  • LPDDR4 SDRAM speeds up to 533 MHz/1066 Mbps for speed grades 8 and 9, and up to 400 MHz/800 Mbps for speed grade 7
    (Dual-rank configurations are supported up to 400 MHz/800 Mbps)
  • Component support for interface data widths of x16 and x32.
  • Up to 16 Gb density support per channel

Jump to

Block Diagram

Memory Controller IP Core Block DiagramExpand Image
  • Memory Controller IP Core Functional Diagram for Avant Devices
  • Consists of 3 main blocks: the Memory Controller, DDRPHY, and Training Engine
  • This figure represents the memory controller submodules and their connectivity
Memory Controller Block DiagramExpand Image
  • Memory Controller IP Core Functional Diagram for Nexus Devices
  • Consists of 3 main blocks: the Memory Controller, PHY, and Training Engine
  • This figure represents the LPDDR4 Memory Controller submodules and its connectivity

Comparison Table

The table below outlines the differences between the Lattice Nexus, Avant and Nexus 2 FPGA families, focusing on aspects such as memory protocols, speed, data widths, and other key specifications.

Lattice Device/Platform Nexus Avant Nexus 2
Memory Protocol LPDDR4 LPDDR4 DDR4 LPDDR4 DDR4
Max Interface Speed 533 MHz / 1066 Mbps 1200 MHz / 2400 Mbps 1200 MHz / 2400 Mbps 1200 MHz / 2400 Mbps 1200 MHz / 2400 Mbps
Single Rank Speed grade 7 – up to 800 Mbps Speed grade 1 – up to 1866 Mbps Speed grade 1 – up to 1866 Mbps Speed grade 1 – up to 1866 Mbps Speed grade 1 – up to 1866 Mbps
Speed grade 8,9 – up to 1066 Mbps Speed grade 2 – up to 2133 Mbps Speed grade 2 – up to 2133 Mbps Speed grade 2 – up to 2133 Mbps Speed grade 2 – up to 2133 Mbps
  Speed grade 3 – up to 2400 Mbps Speed grade 3 – up to 2400 Mbps Speed grade 3 – up to 2400 Mbps Speed grade 3 – up to 2400 Mbps
Dual Rank Up to 800 Mbps only Speed grade 2,3 only Speed grade 2,3 only Speed grade 2,3 only Speed grade 2,3 only
Up to 2133 Mbps (speed grade 2) and Up to 2400 Mbps (speed grade 3) Up to 2133 Mbps (speed grade 2) and Up to 2400 Mbps (speed grade 3) Up to 2133 Mbps (speed grade 2) and Up to 2400 Mbps (speed grade 3) Up to 2133 Mbps (speed grade 2) and Up to 2400 Mbps (speed grade 3)
Supported Data Widths -16, -32 -16, -32, -64 -16, -32, -40, -64, -72 -16, -32 -16, -32, -40
DRAM Configuration x16 x16 x8 x16 x8, x16
Supported Memory Format Component Component Component, UDIMM Component Component

Ordering Information

  Part Number
Device Family Single Seat Perpetual Single Seat Annual
Avant and Nexus 2 (DDR4)
Certus-N2 DDR4-MC-CN2-UT DDR4-MC-CN2-US
Avant-G DDR4-MC-AVG-UT DDR4-MC-AVG-US
Avant-X DDR4-MC-AVX-UT DDR4-MC-AVX-US
Avant-E DDR4-PHY-AVE-UT DDR4-PHY-AVE-US
Avant and Nexus 2 (LPDDR4)
Certus-N2 LPDDR4-MC-CN2-UT LPDDR4-MC-CN2-US
Avant-G LPDDR4-MC-AVG-UT LPDDR4-MC-AVG-US
Avant-X LPDDR4-MC-AVX-UT LPDDR4-MC-AVX-US
Avant-E LPDDR4-PHY-AVE-UT LPDDR4-PHY-AVE-US
Nexus
CertusPro-NX LPDDR4-MC-CPNX-UT LPDDR4-MC-CPNX-US
MachXO5-NX LPDDR4-MC-XO5-UT LPDDR4-MC-XO5-US

To download a full evaluation version of this IP, go to the IP Server in Lattice Radiant. This IP core supports Lattice’s IP hardware evaluation capability, which makes it possible to generate the IP core and operate in hardware for a limited time (approximately four hours) without requiring an IP license.

To find out how to purchase the LPDDR4 IP core, please contact your local Lattice Sales Office.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
Avant LPDDR4 Memory Controller Driver API Reference
FPGA-TN-02379 1.0 8/19/2024 PDF 484.2 KB
CertusPro-NX LPDDR4 Memory Controller Driver API Reference
FPGA-TN-02378 1.1 2/25/2025 PDF 490.9 KB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
LPDDR4 Memory Controller IP Core for Nexus Devices - User Guide
FPGA-IPUG-02127 1.7 4/7/2025 PDF 2.7 MB
DDR Memory Controller IP Core - User Guide
FPGA-IPUG-02208 1.5 4/7/2025 PDF 1.6 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
DDR Memory Controller IP Core - Release Notes
FPGA-RN-02033 1.1 4/7/2025 PDF 259.3 KB
DDR Memory PHY IP Core - Release Notes
FPGA-RN-02072 1.0 4/7/2025 PDF 248 KB
LPDDR4 Memory Controller IP Core for Nexus Devices - Release Notes
FPGA-RN-02057 1.0 4/7/2025 PDF 207.2 KB

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