SPI Flash Memory Controller IP Core

Industry-standard Interface between a CPU and SPI Flash Memory Device

Related Products

Related Applications

The Serial Peripheral Interface (SPI) Flash Memory Controller IP Core provides an industry-standard interface between a central processing unit (CPU) and an off-chip SPI flash memory device.

The controller has two separate ports: Data Port Advanced High-performance Bus (AHB-Lite) interface and Control Port Advanced Peripheral Bus (APB) interface.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Two bus interfaces: Data Port AHB-Lite Subordinate interface and Control Port APB Completer interface
  • Option to individually configure the data bus widths of Data Port and Control Port to 8 or 32 bits
  • Option to configure controller with Page Program Buffer to speed up Page Program
  • Option to configure controller with Page Read Buffer to speed up Page Read
  • Configurable serial clock (sclk_o) frequency

Jump to

Block Diagram

SPI Flash Memory Controller IP Core Block DiagramExpand Image

Ordering Information

The SPI Flash Memory Controller IP Core is available for free to use in Lattice Radiant design software.

Documentation

Quick Reference
Information Resources
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
SPI Flash Memory Controller IP Core - User Guide
FPGA-IPUG-02134 2.1 7/15/2025 PDF 1.9 MB
TITLE NUMBER VERSION DATE FORMAT SIZE
Select All
SPI Flash Memory Controller IP Release Notes
FPGA-RN-02039 1.0 12/20/2024 PDF 216.7 KB

*By clicking on the "Notify Me of Changes" button, you agree to receive notifications on changes to the document(s) you selected.

ABOUT LATTICE

SALES

SUPPORT

FOLLOW