SPI Flash Memory Controller IP Core

Industry-standard Interface between a CPU and SPI Flash Memory Device

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The Serial Peripheral Interface (SPI) Flash Memory Controller IP Core provides an industry-standard interface between a central processing unit (CPU) and an off-chip SPI flash memory device.

The controller has two separate ports: Data Port Advanced High-performance Bus (AHB-Lite) interface and Control Port Advanced Peripheral Bus (APB) interface.

Resource Utilization details are available in the IP Core User Guide.

Features

  • Two bus interfaces: Data Port AHB-Lite Subordinate interface and Control Port APB Completer interface
  • Option to individually configure the data bus widths of Data Port and Control Port to 8 or 32 bits
  • Option to configure controller with Page Program Buffer to speed up Page Program
  • Option to configure controller with Page Read Buffer to speed up Page Read
  • Configurable serial clock (sclk_o) frequency

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Block Diagram

SPI Flash Memory Controller IP Core Block Diagram放大图片

Performance and Size

Avant Family
LAV-AT-500E-3LFG1156I
Configuration ahb_hclk_i Fmax (MHz)1 apb_pclk_i Fmax (MHz)1 Registers LUTs2 EBR
Default 263.3 116.23 963 1379 0
Enable Page Program Buffer: Checked,
Enable Page Read Buffer: Checked,
Others = Default		 220.17 112.32 1051 1980 0
Enable Page Program Buffer: Checked,
Page Program Buffer Memory Type: EBR,
Others = Default		 220.17 110.51 1010 1490 1
Enable Page Read Buffer: Checked,
Page Read Buffer Memory Type: EBR,
Others = Default		 211.78 101.17 1011 1480 1
Enable Page Program Buffer: Checked,
Enable Page Read Buffer: Checked,
Page Buffer Interface: AHBL,
SCLK Rate: 15,
Others = Default		 154.58 101.17 1031 2007 0

1. Fmax is generated when the FPGA design only contains SPI Flash Controller IP Core, and the target frequency is 100 MHz for ahb_hclk_i and 50 MHz for apb_pclk_i. These values may be reduced when user logic is added to the FPGA design.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

LAV-AT-500E-1LFG1156I
Configuration ahb_hclk_i Fmax (MHz)1 apb_pclk_i Fmax (MHz)1 Registers LUTs2 EBR
Default 190.99 98.53 963 1379 0
Enable Page Program Buffer: Checked,
Enable Page Read Buffer: Checked,
Others = Default		 185.81 94.72 1051 1980 0
Enable Page Program Buffer: Checked,
Page Program Buffer Memory Type: EBR,
Others = Default		 192.16 98.08 1010 1490 1
Enable Page Read Buffer: Checked,
Page Read Buffer Memory Type: EBR,
Others = Default		 170.62 91 1011 1480 1
Enable Page Program Buffer: Checked,
Enable Page Read Buffer: Checked,
Page Buffer Interface: AHBL,
SCLK Rate: 15,
Others = Default		 146.65 98.99 1031 2007 0

1. Fmax is generated when the FPGA design only contains SPI Flash Controller IP Core, and the target frequency is 100 MHz for ahb_hclk_i and 50 MHz for apb_pclk_i. These values may be reduced when user logic is added to the FPGA design.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

Nexus Family
LFMXO5-25-9BBG400C
Configuration ahb_hclk_i Fmax (MHz)1 apb_pclk_i Fmax (MHz)1 Registers LUTs2 EBR
Default 200 167.62 963 1367 0
Enable Page Program Buffer: Checked,
Enable Page Read Buffer: Checked,
Others = Default		 200 200 1051 2147 0
Enable Page Program Buffer: Checked,
Page Program Buffer Memory Type: EBR,
Others = Default		 200 186.67 1010 1477 1
Enable Page Read Buffer: Checked,
Page Read Buffer Memory Type: EBR,
Others = Default		 200 155.23 1011 1474 1
Enable Page Program Buffer: Checked,
Enable Page Read Buffer: Checked,
Page Buffer Interface: AHBL,
SCLK Rate: 15,
Others = Default		 163.03 187.51 1031 2143 0

1. Fmax is generated when the FPGA design only contains SPI Flash Controller IP Core, and the target frequency is 100 MHz for ahb_hclk_i and 50 MHz for apb_pclk_i. These values may be reduced when user logic is added to the FPGA design.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

LFMXO5-25-7BBG400C
Configuration ahb_hclk_i Fmax (MHz)1 apb_pclk_i Fmax (MHz)1 Registers LUTs2 EBR
Default 152.46 114.22 963 1370 0
Enable Page Program Buffer: Checked,
Enable Page Read Buffer: Checked,
Others = Default		 136.52 138.03 1051 2140 0
Enable Page Program Buffer: Checked,
Page Program Buffer Memory Type: EBR,
Others = Default		 154.51 110.79 1010 1471 1
Enable Page Read Buffer: Checked,
Page Read Buffer Memory Type: EBR,
Others = Default		 131.56 101.55 1011 1473 1
Enable Page Program Buffer: Checked,
Enable Page Read Buffer: Checked,
Page Buffer Interface: AHBL,
SCLK Rate: 15,
Others = Default		 103.16 114.53 1031 2146 0

1. Fmax is generated when the FPGA design only contains SPI Flash Controller IP Core, and the target frequency is 100 MHz for ahb_hclk_i and 50 MHz for apb_pclk_i. These values may be reduced when user logic is added to the FPGA design.
2. The distributed RAM utilization is accounted for in the total LUT4s utilization. The actual LUT4 utilization is distribution among logic, distributed RAM, and ripple logic.

Ordering Information

The SPI Flash Memory Controller IP Core is available for free to use in Lattice Radiant design software.

Documentation

快速参考
标题 编号 版本 日期 格式 文件大小
选择全部
SPI Flash Memory Controller IP Core – User Guide
FPGA-IPUG-02134 1.9 6/28/2024 PDF 1.9 MB

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