SPI Flash Memory Controller IP Core

Serial Peripheral Interface Flash Memory Controller

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The SPI Flash Memory Controller IP Core provides an industry-standard interface between a central processing unit (CPU) and an off-chip SPI flash memory device.

The controller has two separate slave ports: Data Port AHB-lite interface and Control Port APB interface. Data Port can be used by the CPU to read from, or write to, any memory location within the SPI flash.

Features

  • Two slave interfaces: Data Port AHB-lite interface and Control Port APB interface
  • Option to enable/disable Control Port
  • Option to individually configure the data bus widths of Data Port and Control Port to 8 or 32 bits
  • Option to configure controller with Page Program/Read Buffer to speed up Page Program/Read
  • Configurable serial clock (sclk_o) frequency, SPI flash sector size, SPI flash page size and SPI flash command set

Jump to

Block Diagram

Performance and Size

This table shows configuration and resource utilization for LIFCL-40-8BG400I using Synplify Pro of Lattice Radiant software 2.1.
Control Port APB Datawidth AHB-lite Datawidth Clk Fmax (MHz)* Registers LUTs EBRs
ENABLED 32 32 200 473 1096 0
DISABLED 32 8 200 88 162 0
DISABLED 32 32 200 174 331 0

Ordering Information

The SPI Flash Memory Controller IP Core is available for free to use in Lattice Radiant design software.

Documentation

快速参考
标题 编号 版本 日期 格式 文件大小
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SPI Flash Memory Controller IP Core - Lattice Radiant Software
FPGA-IPUG-02134 1.2 5/31/2022 PDF 690.9 KB
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