The MachXO5T-NX Development Board features the LFMXO5-100T device in a 400-ball caBGA package. This device offers a variety of features and programmability that enhances Secure Control PLD functionality with Multiple Boot and PCI Express. Its cryptographic engine supports user-mode security features. Along with the cryptographic engine, numerous system functions are included such as four PLLs and 3,744 kbits of embedded RAM plus hardened implementations of I2C and SPI, LFMXO5-100T FPGAs feature one hard PCIe link layer IP block which supports PCIe Gen1, Gen2 with 1 or 2 x1 configuration, with flexible, high performance I/O support numerous single-ended and differential standards including LPDDR4 controller and SLVS.