MachXO5T-NX Development Board

Enhances Secure Control PLD Functionality with Multiple Boot and PCI Express

The Lattice Semiconductor MahXO5T™-NX Development Board allows you to investigate and experiment with the features of the LFMXO5-100T device. The features of the MachXO5T-NX Development Board can assist you with the rapid prototyping and testing of your specific designs.

The MachXO5T-NX Development Board features the LFMXO5-100T device in a 400-ball caBGA package. This device offers a variety of features and programmability that enhances Secure Control PLD functionality with Multiple Boot capabilities. Its cryptographic engine supports user-mode security features. Along with the cryptographic engine, numerous system functions are included such as four PLLs and 3,744 kbits of embedded RAM plus hardened implementations of I2C and SPI, LFMXO5-100T FPGAs feature one hard PCIe link layer IP block which supports PCIe Gen1, Gen2 with 1 or 2 x1 configuration, with flexible, high performance I/O support numerous single-ended and differential standards including LPDDR4 controller and SLVS.

Optional SMA to Support ×1 PCIe – The First Lattice Control FPGA which supports PCIe Gen 2 with a high bandwidth control path of 5 Gpbs and offers 2 PCIe ports (1 channel per port). This control FPGA is driving PCIe-enabled CPU/SoC control functions in Industrial, Server Computing, and Communications.

ADC Interface with 10K POT - There are two dedicated ADC input pairs for LFMXO5-100T. This board provides multiple application options. For default population, one pair of ADC0 is used to measure the core VCC voltage drop through a 10 mΩ resistor R112. Therefore, the core VCC current is calculable. Positive input of another pair ADC1 is connected to a 10 kΩ Trimmer Potentiometers (POT1) which provides voltage variation from 0 V to selectable VCCIO4 and the negative input of ADC1 is grounded through 1 kΩ resistor.

Optional Aardvark Header – The Aardvark I2C /SPI Host Adapter is a fast and powerful I2C bus and SPI bus host adapter through USB. It allows you to interface a Windows, Linux, or Mac OS X PC through USB to a downstream embedded system environment and transfer serial messages using the I2C and SPI protocols.


  • Supports PCIe Gen2 x1 Edge Connector
  • Supports LPDDR4 up to 1066Mbps, x16 bits
  • Two Gbe PHY RJ45 connectors, with SGMII PHY support
  • Versa Headers bridge with Lattice ASC Demo Board to support L-ASC10
  • General Purpose Input/Output (GPIO) interface with PMOD, Arduino and Raspberry Pi boards

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Board Photos

Bottom View

Side View

Ordering Information

  • Ordering Part Number: LFMXO5-100T-EVN
  • Click here to find an authorized Lattice distributor near you


Quick Reference
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MachXO5T-NX Development Board - Quick Start Guide
QS070 1.0 4/18/2023 PDF 543.3 KB
MachXO5T-NX Development Board - User Guide
FPGA-EB-02058 1.0 4/18/2023 PDF 3.5 MB

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